When you look at a standard thermal-magnetic breaker in your home panel, the internal mechanism is purely mechanical: a bimetallic strip for inverse-time overloads and a solenoid for instantaneous short circuits. But if you pull the schematic diagram of a circuit breaker designed for modern DC solar arrays, LiFePO4 battery banks, or smart subpanels, you will find an entirely different architecture. Electronic Trip Units (ETUs) and solid-state breakers replace moving parts with shunt resistors, comparators, and MOSFETs to achieve microsecond clearing times and precise $I^2t$ let-through energy limiting.
This guide decodes the schematic diagram of an electronic DC circuit breaker. We will walk through the exact topology, assign real component values for a 12V/10A branch circuit, analyze the failure modes, and show you how to breadboard-test the design before committing it to a PCB or deploying it in a low-voltage home power system.
Decoding the Schematic Diagram of a Circuit Breaker: Thermal vs. Electronic
Why choose an electronic topology over a traditional thermal-magnetic breaker? In AC home wiring, alternating current naturally crosses zero 120 times a second (in a 60Hz system), which helps extinguish the arc when the breaker contacts separate. DC current has no zero-crossing. When a thermal-magnetic breaker trips under a heavy DC fault, the resulting arc can weld the contacts shut or destroy the breaker housing.
An electronic solid-state breaker solves this by using a semiconductor switch (like a MOSFET) that turns off in nanoseconds, completely avoiding mechanical arcing. Furthermore, electronic topologies allow for precise, adjustable trip curves. According to NFPA 70 (National Electrical Code) Article 240, overcurrent devices must be rated for the specific voltage and current of the system; solid-state breakers designed with the correct schematic topology easily meet these requirements for low-voltage DC applications while offering smart-panel telemetry that mechanical breakers cannot provide.
Electronic Trip Topology: Node Labels and Component Walkthrough
Let us design a 10A solid-state DC breaker for a 12V nominal (11.5V–14.4V actual) home battery branch circuit. The schematic relies on high-side current sensing and an open-drain comparator driving a P-channel MOSFET.
Topology and Node Definitions
- Node A (Source IN): 12V DC from the battery bus.
- Node B (Sense Node): The junction between the current shunt and the MOSFET source.
- Node C (Load OUT): The MOSFET drain, feeding the branch circuit.
- Node D (Reference): The non-inverting input of the comparator, setting the trip threshold.
Component Selection and Real Values
To trip at exactly 10A, we need a sense voltage that the comparator can reliably read without wasting excessive power as heat.
- R1 (Current Shunt): 10mΩ (0.01Ω), 5W power rating. At 10A, the voltage drop across R1 is $V = I \times R = 10A \times 0.01\Omega = 100mV$. Power dissipated is $I^2R = 1W$, well within the 5W rating.
- Q1 (Switching Element): IRF9540N P-Channel MOSFET. It has a $V_{DS}$ rating of -55V and an $R_{DS(on)}$ of roughly 20mΩ. At 10A, it will dissipate about 2W and requires a small extruded aluminum heatsink.
- U1 (Comparator): LM393 dual comparator. It operates from a single supply and features an open-collector output, which is critical for our gate-drive topology.
- R2 & R3 (Reference Divider): We need exactly 100mV at Node D to match the 10A trip point. Using a stable 5V LDO (like an LM7805) fed from Node A, we use R2 = 1kΩ and R3 = 49kΩ to divide 5V down to roughly 100mV.
- R4 (Gate Pull-up): 10kΩ resistor tied between Node A and the gate of Q1. Because the LM393 can only pull its output to ground (open-collector), this resistor is required to pull the gate high (turning the MOSFET off) when the comparator trips.
For a deeper look at how integrated versions of this topology are handled in commercial silicon, Texas Instruments' overview on eFuses and solid-state switches demonstrates how these exact discrete nodes are miniaturized into single IC packages for modern telecom and DC home panels.
Failure Mode Contrast: What Breaks at the Extremes?
A schematic is only as good as its failure analysis. In home electrical design, we must assume components will fail. Here is the behavior matrix detailing what happens when individual elements in our topology short or open.
| Component | Failure Mode | Effect on Node B (Sense) | Effect on Node C (Load) | Breaker State & Hazard |
|---|---|---|---|---|
| R1 (Shunt) | Short Circuit | Drops to 0V regardless of current | Remains powered | Fails Closed: Breaker will never trip. Upstream main fuse must clear the fault. |
| R1 (Shunt) | Open Circuit | Floats or drops to 0V (if pull-down present) | Power interrupted | Nuisance Trip / Dead: Load loses power immediately. |
| Q1 (MOSFET) | Drain-Source Short | Unchanged | Hard tied to Node A | Fails Closed (Catastrophic): Breaker is bypassed. Wire insulation may melt if upstream protection fails. |
| U1 (Comparator) | Output stuck Low | Unchanged | Remains powered | Fails Closed: Gate is perpetually pulled to GND, keeping Q1 ON regardless of overcurrent. |
| R4 (Pull-up) | Open Circuit | Unchanged | Remains powered | Fails Closed: When U1 trips (goes high-Z), the gate has no path to Node A. Q1 stays ON. |
Breadboard-Testing the Solid-State Breaker Step-by-Step
Before wiring this into a 48V solar combiner box, you must validate the trip threshold on the bench. Do not skip the decoupling steps; high di/dt faults will cause comparator chatter without them.
- Build the Reference and Logic Supply: Wire the LM7805 to a bench supply set to 12V. Connect R2 (1kΩ) and R3 (49kΩ) to the 5V output. Measure Node D with your multimeter; it should read exactly 0.100V (100mV). Place a 100nF ceramic capacitor across the 5V and GND rails to prevent logic noise.
- Wire the Shunt and Sense Lines: Insert the 10mΩ shunt in series with the positive rail from your bench supply. Connect the inverting input (Pin 2) of the LM393 to the load-side of the shunt (Node B). Crucial: Use Kelvin sensing (separate wires for the current path and the sense path) even on a breadboard to avoid measuring the voltage drop of the breadboard contacts.
- Configure the Gate Drive: Connect the LM393 output (Pin 1) to the gate of the IRF9540N. Wire R4 (10kΩ) between the source of the MOSFET (Node B) and the gate. Connect the drain to your test load.
- Establish the Baseline: Turn on the bench supply. The LM393 sees 100mV at the inverting input and 100mV at the non-inverting input. With a slight imbalance, the output should be high-impedance, allowing R4 to pull the gate high, turning the P-MOSFET off. To turn it on initially, you may need to momentarily pull the non-inverting input slightly higher than the inverting input, or add a small hysteresis network (a 1MΩ feedback resistor from Pin 1 to Pin 3) to ensure a clean power-on state.
- Inject the Fault: Connect an electronic load to Node C. Slowly ramp the current draw from 0A to 12A. Watch the multimeter on Node C. At exactly 10A (when the shunt drop exceeds 100mV), the LM393 output will snap to ground, pulling the MOSFET gate low and instantly cutting power to the load.
- Verify Reset Behavior: Remove the short/overload. The comparator should release, the gate pulls high via R4, and power is restored. If it latches off, you have successfully implemented a trip-and-lockout topology (common in smart panels requiring manual resets).
Frequently Asked Questions
How do you read a schematic diagram of a circuit breaker for a smart panel?
Smart panel breakers use the same fundamental electronic trip topology outlined above, but they add a microcontroller (like an ESP32 or STM32) between the shunt and the gate driver. Instead of a pure analog comparator, the microcontroller reads the shunt voltage via an ADC, calculates the RMS current and $I^2t$ thermal accumulation in software, and triggers a digital GPIO pin to drive the MOSFET or a mechanical relay latch. When reading these schematics, look for the ADC input pins and the isolated gate-driver ICs (like the Si823x series) that protect the low-voltage logic from the high-voltage bus.
What is the difference between a thermal and electronic schematic diagram of a circuit breaker?
A thermal-magnetic schematic is essentially a single-line diagram showing a bimetallic element in series with a magnetic trip coil, both acting on a mechanical latch. There are no active semiconductor nodes, no ground references for logic, and no power supplies. An electronic schematic, conversely, requires a complete low-voltage DC power supply (to run the op-amps or microcontrollers), a precision current-sense element (shunt or Hall-effect sensor like the ACS712), and a solid-state or solenoid-driven output stage. Electronic schematics are significantly more complex but offer programmable trip curves that thermal schematics cannot achieve.
Can I use a standard AC breaker schematic for a DC solar battery bank?
No. Standard AC thermal-magnetic breakers are not rated for DC voltage. The internal arc chutes and contact gaps in an AC breaker are designed to rely on the AC zero-crossing to extinguish arcs. If you use a 120V AC breaker on a 48V or 96V DC battery bank, a short circuit will sustain a continuous DC arc inside the breaker, leading to a panel fire. You must use breakers specifically rated for DC (with larger contact gaps and magnetic blowouts) or implement the solid-state electronic topology detailed in this guide, backed by a DC-rated Class T or ANL fuse.
