The strict arc fault circuit interrupter definition per NEC Article 100 is "a device that provides protection from the effects of arc faults by recognizing characteristics unique to arcing and by functioning to de-energize the circuit when an arc fault is detected." In residential AC wiring, this translates to off-the-shelf AFCI breakers from brands like Square D or Eaton. But in the embedded and renewable energy space—specifically 48V DC solar arrays and LiFePO4 battery banks—DC arc faults lack the natural zero-crossings that extinguish AC arcs. A sustained DC arc can easily exceed 5,000°C, igniting surrounding insulation in seconds.

Because commercial DC AFCI breakers are expensive and often proprietary, embedded engineers frequently build custom Arc Fault Detection Devices (AFDD) using microcontrollers. This guide translates the core arc fault circuit interrupter definition into a practical, bench-testable analog front-end (AFE) topology for an ESP32, designed to isolate the high-frequency broadband "hiss" of a DC arc from a massive DC baseline current.

Safety Warning: DC arc faults involve extreme heat and fire risk. Never intentionally generate high-current DC arcs outside of a controlled, fire-suppressed laboratory environment. The breadboard testing procedure below uses low-voltage signal injection to simulate arc signatures safely. Always use proper fusing on high-current DC bus lines.

The Arc Fault Circuit Interrupter Definition: AC vs. DC Realities

While the foundational arc fault circuit interrupter definition applies to both current types, the physics of detection differ wildly. AC arcs extinguish 120 times a second (on a 60Hz grid) and reignite if the gap is small enough, creating a distinct "shoulder" in the current waveform. Commercial AC AFCIs look for this waveform distortion and high-frequency noise.

DC arcs, once struck, sustain continuously. The primary signature of a DC series arc is not waveform distortion, but broadband high-frequency noise (typically 10 kHz to 100 kHz) superimposed on the DC current baseline. To detect this with an ESP32, we cannot simply read the raw current; a 50A baseline will saturate the ADC, and the 10mV arc noise will be lost in the ESP32’s inherent SAR ADC noise floor. We need an analog topology that strips the DC and amplifies only the AC noise.

AFE Topology for ESP32 Arc Signature Extraction

To bridge the gap between a high-current DC bus and the ESP32’s 0–3.1V ADC window, we use a high-pass filter coupled with a non-inverting operational amplifier. This topology isolates the arc signature before the microcontroller ever sees it.

Node Topology Description

  • Node A (Shunt Vout): The raw differential voltage across the high-current shunt resistor. Contains the massive DC baseline + microvolt-level arc noise.
  • Node B (HPF In): The output of the series coupling capacitor. The DC baseline is blocked; only the AC arc noise passes.
  • Node C (Op-Amp +In): The biased non-inverting input of the op-amp, sitting at a 1.65V DC offset to allow the AC signal to swing symmetrically.
  • Node D (ADC In): The amplified, filtered output feeding directly into the ESP32 GPIO34 (an input-only pin with an 11dB attenuation path for a 0–3.1V range).
Table 1: AFE Component Specification & Topology Roles
Designator Value / Part Number Tolerance / Rating Topology Role & Behavior
R_Shunt 1.5 mΩ (Custom Manganin) 1%, 5W Generates 75mV drop at 50A. Provides Node A raw signal.
C1 (Coupling) 100 nF (Polypropylene Film) 5%, 50V Blocks DC baseline. Forms high-pass filter with R1. Passes >10kHz.
R1 (Bias) 10 kΩ (Metal Film) 1%, 1/4W Pulls Node B/C to the 1.65V bias voltage. Sets HPF cutoff with C1.
R2 (Feedback) 47 kΩ (Metal Film) 1%, 1/4W Sets non-inverting gain. Gain = 1 + (R2/R3) = ~5.7x.
R3 (Ground) 10 kΩ (Metal Film) 1%, 1/4W Completes the feedback divider to GND for the op-amp.
U1 (Op-Amp) MCP6002 (Dual, R2R) 1 MHz GBW, 5V VCC Amplifies the high-passed noise to fill the ESP32 ADC window.

Component Selection and Design Walkthrough

Why choose this active hardware high-pass topology over the alternative? The common alternative is to use a high-resolution external ADC (like the ADS1115) and perform a Fast Fourier Transform (FFT) or digital IIR high-pass filter purely in ESP32 software.

The problem with the software-only approach is aliasing and dynamic range. If your DC bus has 50A of current and a 50A arc fault introduces 20mV of high-frequency noise, a 16-bit ADC measuring a 75mV full-scale shunt drop will only allocate a handful of bits to the noise. Furthermore, the ESP32’s internal I2S or I2C bandwidth limits how fast you can sample to catch 100kHz transients. By using the MCP6002 and a 100nF film capacitor at Node B, we physically strip away the 50A DC baseline. The op-amp then applies a 5.7x gain exclusively to the AC noise, mapping a 20mV arc signature to a ~114mV swing centered at 1.65V. This easily clears the ESP32 SAR ADC noise floor without requiring external digital conversion.

We select a Polypropylene film capacitor for C1 rather than a ceramic X7R. Ceramic capacitors exhibit piezoelectric effects and microphonics; physical vibration from a contactor closing nearby can generate false voltage spikes that mimic arc noise. Film capacitors are immune to this microphonic interference.

Failure Modes: What Breaks at the Extremes?

When designing safety-critical embedded topologies, you must analyze what happens when passive components fail. The NEC arc fault circuit interrupter definition implies the device must fail-safe or alert upon internal fault. Here is the behavior matrix for our AFE topology.

Table 2: Topology Failure Mode & Behavior Contrast
Fault Condition Node Impact ESP32 ADC Reading (GPIO34) System Result & Mitigation
C1 Fails Open Node B floats; no AC signal reaches Node C. Steady ~2048 (1.65V bias). Blind to arcs. Mitigation: ESP32 watchdog injects a 20kHz test tone via a MOSFET; if ADC doesn't see it, trigger alarm.
C1 Fails Short DC baseline from Node A floods Node C. Pegged at 4095 (3.1V+ rail saturation). False positive / Saturation. Mitigation: Software detects continuous max-ADC state and flags "Sensor Fault".
R2 Fails Open Op-amp loses feedback; gain drops to 1 (buffer). Noise signal is 5.7x smaller than designed. Reduced sensitivity. Small arcs missed. Mitigation: Periodic self-test tone amplitude verification.
Shunt R_Shunt Opens Main DC circuit breaks. Node A drops to 0V. Steady ~2048 (1.65V bias). Load loses power. Arc impossible. System safely de-energized.

Notice the contrast between C1 failing open versus short. An open coupling cap silently disables the detector, which is why the NFPA 70 (NEC) requires supervisory circuits in life-safety gear. Our mitigation relies on the ESP32 generating a known high-frequency PWM signal, coupling it into the shunt via a high-value resistor, and verifying the ADC sees the expected amplified amplitude at Node D.

Breadboard Testing and Calibration Steps

Do not test this by striking a physical arc on your bench. Instead, we simulate the broadband noise signature of an arc using a secondary microcontroller or function generator to inject high-frequency noise into Node A.

Bench Tip: If you don't have a function generator, use a second Arduino Nano. Write a script that rapidly toggles a digital pin through a 1kΩ resistor into Node A. The sharp square-wave edges contain the high-frequency harmonics needed to simulate arc "hiss."
  1. Power the AFE: Connect the MCP6002 VCC to a clean 5V supply and GND to your breadboard ground. Do not power the ESP32 yet.
  2. Establish the Bias: Using a voltage divider (two 10kΩ resistors from 5V to GND), create a 2.5V reference. (Note: We use 2.5V for the op-amp bias, but the ESP32's internal 11dB attenuation maps 3.1V to 4095, so 2.5V sits safely at an ADC reading of ~3300, leaving headroom for the AC swing).
  3. Inject the Signal: Connect your function generator (or Arduino PWM injector) to Node A. Set it to a 50 kHz sine or square wave, 20mV peak-to-peak.
  4. Verify Node B: Probe Node B with an oscilloscope. You should see the 20mV AC signal centered exactly at 0V (the DC block is working).
  5. Verify Node C: Probe Node C. You should now see the 20mV AC signal centered at your 2.5V bias voltage.
  6. Measure Node D: Probe the op-amp output. The 20mV signal should be amplified by 5.7x, resulting in a ~114mV peak-to-peak swing centered at 2.5V.
  7. ESP32 Integration: Power the ESP32. Connect Node D to GPIO34. Upload a simple analogRead() loop printing to the serial monitor at 115200 baud.
  8. Software Baseline: With the injector OFF, the serial monitor should read a steady value around 3300 (±15 counts of ESP32 ADC jitter). Turn the injector ON; you will see the values rapidly fluctuate between ~3150 and ~3450. This fluctuation is your arc signature trigger threshold.

By physically separating the DC baseline from the AC fault signature at the component level, you honor the core intent of the arc fault circuit interrupter definition: reliable, rapid identification of arcing characteristics. This hardware topology ensures your ESP32 spends its clock cycles analyzing genuine fault data rather than fighting its own ADC limitations.