The ESP32-C3 Mini form factor—encompassing the generic "SuperMini", WeAct C3 Core, and Lolin C3 Mini—packs the single-core RISC-V ESP32-C3FH4 chip into a breadboard-friendly footprint. While the silicon inside is identical, the silkscreen and broken-out pins vary wildly between manufacturers. The direct answer to your pinout needs is below: this master table maps the 22 usable GPIOs to their primary functions, bypassing the confusing clone-board markings.

Master ESP32-C3 Mini Pinout Reference

Unlike standard electrical wiring governed by regional codes (NEC vs. IEC), microcontroller pinouts are dictated by the silicon datasheet and the board manufacturer's reference design. The table below reflects the official Espressif ESP32-C3 silicon standard, annotated for how these pins actually appear on Mini-class dev boards.

Pin / GPIO Primary Function Secondary / Mux Functions Mini Board Notes & Constraints
GPIO0 ADC1_CH0 / I2S XTAL_32K_N 12-bit ADC. Do not use for digital input if ADC is active.
GPIO1 ADC1_CH1 / I2S XTAL_32K_P 12-bit ADC. Shared with external 32kHz crystal footprint.
GPIO2 ADC1_CH2 / SPI Strapping Pin Strapping: Must be LOW at boot for SPI flash. Avoid external pull-ups.
GPIO3 ADC1_CH3 General I/O 12-bit ADC. Safe for general digital I/O.
GPIO4 ADC1_CH4 / SPI General I/O 12-bit ADC. Often used for battery voltage dividers.
GPIO5 ADC2_CH0 / I2C General I/O ADC2 is disabled when WiFi is active. Use for I2C SDA instead.
GPIO6 I2C SCL / SPI UART1_TX Default I2C clock line on most ESP-IDF configurations.
GPIO7 I2C SDA / SPI UART1_RX Default I2C data line. Safe for external sensors.
GPIO8 General I/O Strapping Pin / Debug TX Strapping: Controls boot log output. Keep floating or LOW for normal boot.
GPIO9 General I/O Strapping Pin / Boot Mode Strapping: Must be HIGH for normal SPI boot. Pulled HIGH internally.
GPIO10 SPI_FSPICS0 General I/O / PWM Often broken out for external SPI displays (CS pin).
GPIO11 - 17 SPI Flash / PSRAM None Unusable: Internally routed to the 4MB Flash / PSRAM. Not broken out.
GPIO18 USB D- (Native) General I/O Routes to USB-C. Must be HIGH at boot for USB-JTAG mode.
GPIO19 USB D+ (Native) General I/O Routes to USB-C. Must be HIGH at boot for USB-JTAG mode.
GPIO20 UART0_RX General I/O Routed to onboard UART bridge (if present) or broken out.
GPIO21 UART0_TX General I/O Routed to onboard UART bridge (if present) or broken out.

Board Variants: SuperMini vs WeAct vs Lolin

When interpreting pinout markings, you must know which board standard you are holding. The "ESP32-C3 Mini" is not a single official product; it is a footprint category. Here is how the three dominant 2026 variants differ in hardware design and silkscreen reliability.

Feature Generic "SuperMini" WeAct C3 Core Board Lolin C3 Mini
USB Interface Native USB (GPIO18/19) direct to port. No UART bridge. Native USB + optional UART bridge depending on batch. Native USB (GPIO18/19). No UART bridge.
Antenna Design PCB trace (often detuned or blocked by battery pads). PCB trace + IPEX/U.FL connector for external antenna. PCB trace + ceramic chip antenna options.
Silkscreen Standard Factory-specific. Often omits GPIO numbers, uses only "D1, D2". Espressif-aligned. Clear GPIO numbering and function labels. Wemos/Lolin standard. Uses "D" numbering mapped to GPIOs.
5V Tolerance None. 3.3V logic only. No protection diodes. None. 3.3V logic only. None. 3.3V logic only.
Best Use Case Ultra-cheap, space-constrained IoT nodes (with external antenna mod). Reliable prototyping, battery-powered nodes requiring RF reliability. Ecosystem integration (Lolin shields, standard Wemos footprints).

The Rows People Get Wrong & Faded Silkscreen Recovery

Even with the table above, bench mistakes happen. Here are the specific pins that cause boot loops or dead shorts, followed by how to recover when your board's silkscreen has rubbed off.

Rows People Get Wrong

  • GPIO18/19 vs GPIO20/21 (The USB Confusion): On the generic SuperMini, the USB-C port is wired directly to GPIO18 (D-) and GPIO19 (D+) for native USB CDC/JTAG. There is no CP2102 or CH340 UART bridge. If you try to flash via UART using GPIO20/21, it will fail unless you manually wire an external FTDI adapter to those pins and hold GPIO9 LOW during reset.
  • GPIO8 (The Boot Log Trap): GPIO8 outputs the ROM boot log by default. If you wire a relay or MOSFET to GPIO8 and it triggers on a brief HIGH pulse at startup, your circuit will activate unexpectedly every time the ESP32 reboots. Always use GPIO4-GPIO7 for startup-sensitive actuators.
  • ADC2 (GPIO5) with WiFi: The ESP32-C3 silicon shares ADC2 hardware with the WiFi/BLE radio. If you initialize WiFi in your code, ADC2 readings on GPIO5 will return garbage or block the thread. Stick to ADC1 (GPIO0-GPIO4) for analog sensing in IoT applications.

Safe Interpretation When Markings Are Faded or Missing

Cheap clone boards often use low-quality silkscreen ink that flakes off after a few breadboard insertions. If you have an unmarked ESP32-C3 Mini board, use these bench recovery steps to identify the critical rails:

Warning: Never probe for VCC (5V or 3.3V) using a continuity test while the board is powered. Always de-energize the board before performing resistance checks.
  1. Find Ground (GND): Set your multimeter to continuity mode. Place the black probe on the metal shield of the USB-C connector. Probe the header pins with the red probe. Any pin that beeps (reads < 1 ohm) is a GND pin. The USB shield is universally bonded to the system ground plane.
  2. Find 5V Input: With the board unpowered, probe for continuity between the header pins and the input capacitor located immediately behind the USB-C port (usually a 10µF or 22µF ceramic cap). The pin connected to the positive side of this cap is your 5V USB rail.
  3. Find 3.3V Output: Locate the voltage regulator (a small SOT-23-5 or SOT-23-3 chip near the USB port). Pin 1 or 3 (depending on the exact LDO part) will be the 3.3V output. Trace the copper pour from the output pin to the nearest header pad.
  4. Identify Native USB (GPIO18/19): Look for two 5.1kΩ pull-down resistors near the USB-C port. The traces from the center USB data pins (CC1/CC2 or D+/D- depending on the exact USB-C implementation on the clone) will route through series resistors directly to GPIO18 and GPIO19.

Hardware Limits & 2026 Design Gotchas

When designing shields or permanent soldered projects around the ESP32-C3 Mini, keep these silicon and physical limitations in mind.

Current Sourcing Limits: The ESP32-C3FH4 can source or sink a maximum of 40mA per GPIO, but the total combined current across all GPIOs must not exceed 150mA. If you are driving multiple LEDs, use a logic-level MOSFET (like the BSS138 or IRLZ44N) rather than sourcing directly from the pins. For high-density LED strips, a dedicated driver IC is mandatory.

The SuperMini Antenna Flaw: The most common generic "SuperMini" boards feature a PCB trace antenna located at the bottom edge of the board. In 2024 and 2025, users reported severe WiFi range degradation. This is because the battery connector pads and ground pour placed directly beneath the antenna detune the RF impedance. If you are using a generic SuperMini for a remote sensor, you must either cut the trace and solder an IPEX connector (if the pads exist), or accept a range of less than 10 meters through walls. For reliable RF, the Espressif hardware design guidelines strictly mandate a keep-out zone under the antenna, which the WeAct and Lolin boards respect far better than the cheapest clones.

Logic Level Translation: The ESP32-C3 is strictly a 3.3V logic device. While some pins have internal ESD diodes that might survive a brief 5V spike, feeding 5V from a standard Arduino Uno or a 5V I2C sensor directly into GPIO6 or GPIO7 will degrade the silicon over time and eventually cause a short to VCC. Always use a bidirectional logic level shifter (like the Texas Instruments TXS0108E or a cheap BSS138-based module) when interfacing with 5V peripherals.