In Boolean algebra, the annulment and identity laws—specifically A + 1 = 1 (A OR 1 = 1) and A · 1 = A (A AND 1 = A)—dictate that any logic variable OR'd with a logical HIGH always outputs a HIGH, while any variable AND'd with a HIGH simply passes the variable's original state. If you have ever typed "a 1 1 boolean algebra" into a search engine while debugging a digital circuit, you are likely grappling with how these exact rules govern everything from microcontroller register masking to physical logic gate wiring. Understanding these identities is not just an academic exercise; it is the foundation of preventing floating inputs, optimizing bitwise code, and designing fault-tolerant digital systems.
The Core Math: Annulment and Identity Laws
The most common mistake makers and junior engineers make is applying standard arithmetic to Boolean logic. In arithmetic, 1 + 1 = 2. In Boolean algebra, there is no "2". The system is strictly binary, constrained to 0 (LOW / False) and 1 (HIGH / True). Therefore, Boolean addition represents the logical OR operation, and Boolean multiplication represents the logical AND operation.
When we look at the A + 1 = 1 rule (the Annulment Law for OR), we are stating that if any input to an OR gate is HIGH, the output is guaranteed to be HIGH, regardless of what the other inputs are doing. Conversely, the A · 1 = A rule (the Identity Law for AND) states that a logical HIGH acts as a "pass-through" for an AND gate. The output will strictly mirror the state of variable A.
| Rule Name | Boolean Expression | Logic Gate Equivalent | Practical Meaning |
|---|---|---|---|
| Annulment (OR) | A + 1 = 1 | OR / NOR | A single HIGH input forces the OR output HIGH. |
| Identity (AND) | A · 1 = A | AND / NAND | A HIGH input allows the other input to pass through unchanged. |
| Annulment (AND) | A · 0 = 0 | AND / NAND | A single LOW input forces the AND output LOW. |
| Identity (OR) | A + 0 = A | OR / NOR | A LOW input allows the other input to pass through unchanged. |
For a deeper mathematical breakdown of these postulates, the All About Circuits digital textbook provides an excellent reference on how these laws scale to multi-variable De Morgan's theorems.
Worked Numeric Example: ESP32 GPIO Bitmasking
To see A · 1 = A in action on a real workbench, let us look at how microcontrollers use bitwise operations to manipulate hardware registers. Suppose you are programming an ESP32 and need to update the lower 8 bits of the GPIO_OUT_W1TS_REG (a 32-bit register) without disturbing the upper 24 bits.
You cannot simply write a new value to the register, because that would overwrite the upper bits, potentially toggling pins you are using for I2C or SPI. Instead, you use a bitmask and a bitwise AND operation. Let us use real hexadecimal and binary values:
- Current Register State:
0x00A5F3(Binary:0000 0000 1010 0101 1111 0011) - Target Mask: We want to preserve the upper 24 bits and force the lower 8 bits to
0x00. Our mask is0xFFFF00(Binary:1111 1111 1111 1111 0000 0000).
When the ESP32 executes Register & Mask, it performs a bit-by-bit AND operation. Look closely at the upper 24 bits: every single bit in the mask is a 1. According to the A · 1 = A identity rule, any bit AND'd with 1 retains its original value. Therefore, the upper 24 bits (0x00A5) pass through completely untouched. The lower 8 bits are AND'd with 0, invoking the A · 0 = 0 annulment rule, safely clearing them.
|) when you intend to clear bits. If you OR a register with a mask containing 1s, the A + 1 = 1 rule will force those specific bits HIGH, potentially shorting a pin if it is configured as an output driving a low-side load.
Where You Meet This in Practice: Hardware and PLCs
What do these algebraic rules change in a physical circuit or installation? They dictate how you terminate unused inputs on physical logic ICs to prevent erratic behavior. A floating CMOS input acts like an antenna, picking up electromagnetic interference and causing the gate to oscillate, which destroys the IC via excessive current draw.
If you are using a 3-input AND gate (like the Texas Instruments SN74HC11) but your circuit only requires 2 inputs, you must tie the third input to a fixed logic level. Because of the A · 1 = A rule, you tie the unused input to VCC (Logic 1). This allows your two active signals to pass through the gate unhindered. If you mistakenly tied it to GND (Logic 0), the A · 0 = 0 rule would force the gate's output permanently LOW, rendering the circuit useless.
| Gate Type | Example IC | Unused Input Termination | Governing Boolean Rule |
|---|---|---|---|
| AND | 74HC08 / 74HC11 | Tie to VCC (Logic 1) | A · 1 = A (Pass-through) |
| NAND | 74HC00 / 74HC10 | Tie to VCC (Logic 1) | A · 1 = A (Pass-through, then inverted) |
| OR | 74HC32 | Tie to GND (Logic 0) | A + 0 = A (Pass-through) |
| NOR | 74HC02 / 74HC27 | Tie to GND (Logic 0) | A + 0 = A (Pass-through, then inverted) |
In industrial PLC ladder logic, the exact same rules apply. A normally-closed (NC) contact that is physically wired and permanently closed acts as a Logic 1. If you place it in series with a motor start button (an AND operation), the A · 1 = A rule ensures the NC contact does not inhibit the start button. If you place it in parallel (an OR operation), the A + 1 = 1 rule will force the motor to run continuously, bypassing the start button entirely—a critical safety hazard if misunderstood.
Frequently Asked Questions
Why does A + 1 = 1 in Boolean algebra instead of 2?
Boolean algebra operates strictly on a binary state system representing truth values (True/False) or voltage states (HIGH/LOW). There is no numerical magnitude, only state. If a switch is closed (1) and you OR it with another closed switch (1), the circuit is still just "closed" (1). The concept of "2" requires arithmetic quantity, which does not exist in digital logic evaluation.
How do I physically wire a logic 1 to an unused AND gate input?
For a 5V CMOS IC like the 74HC series, a Logic 1 requires a voltage above the $V_{IH}$ (Input High Voltage) threshold, which is typically 3.15V minimum. You should tie the unused pin directly to the $V_{CC}$ rail (Pin 14 on a standard 14-pin DIP) using a short jumper wire. For added protection against voltage spikes in noisy industrial environments, route the connection through a 1kΩ to 4.7kΩ pull-up resistor to $V_{CC}$.
What is the difference between A + 1 = 1 and A + 0 = A?
A + 1 = 1 is the Annulment Law: an OR gate with a HIGH input is permanently forced HIGH, masking all other inputs. A + 0 = A is the Identity Law: an OR gate with a LOW input acts as a pass-through, allowing the other input to dictate the output state. You use A + 0 = A when you want to disable a specific input without altering the rest of the logic chain.
Does the A * 1 = A rule apply to PLC ladder logic?
Yes, absolutely. In PLC ladder logic, series instructions act as AND gates, and parallel branches act as OR gates. If you have a hardwired jumper (always TRUE / Logic 1) placed in series with a sensor input, the rung evaluates as Sensor AND 1. By the A · 1 = A rule, the PLC ignores the jumper and the rung's continuity depends entirely on the sensor. This is frequently used during machine commissioning to temporarily bypass safety interlocks for testing (though doing so in production is a severe safety violation).
