Decoding the Power Supply Diagram Circuit for Battery Systems
When you sit down to draft a power supply diagram circuit for a 24V battery or solar array, the immediate challenge is bridging the gap between raw, noisy field power and the clean, low-voltage rails required by modern embedded logic. A 24V nominal battery bank is rarely at 24V. Depending on the chemistry and charge state, a 24V LiFePO4 or lead-acid bank will swing from 19V (deep discharge) up to 29.2V (absorption charging), with transient spikes from inductive loads pushing even higher.
For a typical IoT sensor node running an ESP32 and a handful of 3.3V peripherals, you need a 5V rail for actuators or USB peripherals, and a pristine 3.3V rail for the microcontroller. The direct answer for this load is a two-stage topology: a synchronous switching buck converter to step the 19-29V input down to 5V, followed by a low-dropout regulator (LDO) to clean that 5V down to 3.3V.
Linear vs. Switching: Topology Comparison and Heat Math
The debate between linear and switching regulators isn't about which is universally better; it's about matching the topology to your voltage differential and noise tolerance. Below is the exact breakdown of what each topology brings to the bench.
| Criteria | Switching Buck (e.g., MP2315) | Linear LDO (e.g., AP2112) |
|---|---|---|
| Efficiency | 85% - 95% (across wide Vin/Vout gaps) | 30% - 70% (scales directly with Vout/Vin ratio) |
| Heat Profile | Low static heat; thermal load pushed to inductor | High heat if Vin-Vout > 2V; concentrated in silicon die |
| Output Ripple/Noise | 20mV - 50mV p-p (switching frequency noise) | < 5mV p-p (virtually silent, PSRR dependent) |
| BOM Cost & Footprint | $1.50 - $3.00 (requires inductor, bulky caps) | $0.20 - $0.50 (only requires small ceramic caps) |
For our 24V-to-5V step-down, a linear regulator would dissipate (24V - 5V) * 1A = 19 Watts. That is a soldering iron, not a power supply. Switching is mandatory here. However, for the 5V-to-3.3V step-down, the differential is only 1.7V. At low currents, an LDO wins on cost, footprint, and noise elimination, making it the perfect second stage for RF-sensitive microcontrollers.
The Design Example: 24V Solar to 5V/3.3V IoT Node
Here is the exact component-level specification for a robust, field-proven power supply diagram circuit. This design assumes a maximum continuous load of 2A on the 5V rail (relays, small pumps) and 200mA on the 3.3V rail (ESP32 in active TX mode + I2C sensors).
Stage 1: High-Voltage Buck (19V-29V to 5V @ 2A)
- Regulator: MPS MP2315 (SOT23-8). Integrated MOSFETs, 3A max, 1.4MHz switching frequency.
- Inductor: 4.7µH shielded power inductor (e.g., Wurth 7447742047). Must be rated for at least 3.5A saturation current.
- Output Capacitors: 2x 22µF, 10V, X7R ceramic (0805 package). Note: Never use Y5V dielectrics; they lose up to 80% of their capacitance under DC bias.
- Bootstrap Cap: 100nF X7R placed as close to the BST and SW pins as physically possible.
- Expected Ripple: ~25mV peak-to-peak at the switching frequency.
Stage 2: Low-Noise LDO (5V to 3.3V @ 200mA)
- Regulator: Diodes Inc AP2112K-3.3 (SOT23-5). High PSRR (75dB at 1kHz), low quiescent current.
- Dropout Voltage: 250mV maximum at 600mA. At our 200mA load, dropout is roughly 80mV.
- Headroom Math: Vin (5V) - Vout (3.3V) = 1.7V. Since 1.7V is vastly greater than the 80mV dropout requirement, the LDO is fully regulated and will reject the 25mV switching ripple from the buck stage.
- Expected Ripple: < 3mV peak-to-peak. This easily satisfies the Espressif ESP32 Hardware Design Guidelines, which mandate clean 3.3V rails to prevent ADC non-linearity and WiFi brownouts.
Thermal Derating and Protection Headroom
A schematic is only as good as its thermal reality. Let's run the derating math on the AP2112 LDO to ensure it won't trigger its internal thermal shutdown (typically 160°C) when mounted in a sealed outdoor enclosure.
Power Dissipation Calculation:
P_diss = (Vin - Vout) × I_load
P_diss = (5V - 3.3V) × 0.2A = 0.34 Watts
Temperature Rise Calculation:
ΔT = P_diss × θJA
ΔT = 0.34W × 150°C/W = 51°C rise above ambient.
If your sealed enclosure sits in direct sunlight and reaches an internal ambient of 50°C, the silicon junction will sit at 101°C (50 + 51). This is well below the 125°C maximum operating junction temperature, leaving a 24°C safety margin. However, if your 3.3V load spikes to 500mA (e.g., adding a cellular modem), dissipation jumps to 0.85W, causing a 127.5°C rise. At 50°C ambient, your junction hits 177.5°C, and the part will shut down. If you need >300mA on the 3.3V rail, you must either switch to a SOT-223 package, add a dedicated thermal via array under the part, or use a second switching buck.
Decision Tree: Picking Your Regulator Topology
Stop guessing which regulator to drop into your next board layout. Use this decision matrix to lock in your topology based on your specific input/output delta and current draw. For deeper theory on the trade-offs, refer to Texas Instruments' application notes on LDO vs. Buck architectures.
| Condition (If...) | And... | Then Pick This Topology | Concrete Part Recommendation |
|---|---|---|---|
| Vin - Vout > 3V | I_load > 300mA | Switching Buck | MP2315 (up to 3A) or LMR36015 (up to 1.5A, ultra-low EMI) |
| Vin - Vout < 2V | I_load < 300mA | Linear LDO | AP2112K-3.3 (low noise) or TLV75533P (low Iq) |
| Vin - Vout > 3V | Noise-sensitive load (ADC/RF) | Buck + LC Filter OR Buck + LDO | MP2315 followed by AP2112 (as detailed in this article) |
| Vin can be above OR below Vout | Battery drain to depletion | Non-Inverting Buck-Boost | TPS63020 (handles 1.8V to 5.5V input, outputs 3.3V) |
By treating your power supply diagram circuit as a calculated system of thermal headroom, dielectric derating, and topology matching—rather than just copying a reference schematic—you ensure your 24V solar nodes survive the absorption-charge spikes and keep your RF transceivers online through the night.
