When you are drafting a schematic or debugging a breadboard, the truth table symbols and meanings map directly to two dominant standards: the ANSI/IEEE Std 91-1984 (distinctive shapes) and the IEC 60617 (rectangular outlines). The direct answer for 90% of hobbyist and commercial PCB designers in North America is to use the ANSI/IEEE 91 distinctive shapes, as this is the default library in Altium, KiCad, and Eagle. If you are programming European PLCs or using EPLAN, you must use the IEC 60617 rectangular symbols.

Below is the complete, bookmark-ready reference chart, followed by the decision paths and hardware realities that a basic truth table leaves out.

The Master Logic Gate Symbol and Truth Table Chart

How to read this table: The "ANSI Symbol" column describes the traditional distinctive shapes used in US-based schematic capture. The "IEC 60617" column describes the rectangular symbols mandated in European industrial diagrams. The "Truth Table (Inputs A, B)" column shows the binary output (Y) for all four possible input combinations (00, 01, 10, 11). Source standards: IEEE Std 91-1984 / IEC 60617-12.
Table 1: Complete Logic Gate Symbols, Expressions, and Truth Tables (IEEE 91 / IEC 60617)
Gate Function ANSI/IEEE 91 Shape IEC 60617 Symbol Boolean Expression Truth Table (A,B → Y)
AND D-shaped flat back Rectangle with "&" Y = A · B 00→0, 01→0, 10→0, 11→1
OR Curved shield shape Rectangle with "≥1" Y = A + B 00→0, 01→1, 10→1, 11→1
NOT (Inverter) Triangle with bubble Rectangle with "1" and bubble Y = A' 0→1, 1→0
NAND D-shape with output bubble Rectangle with "&" and bubble Y = (A · B)' 00→1, 01→1, 10→1, 11→0
NOR Curved shield with bubble Rectangle with "≥1" and bubble Y = (A + B)' 00→1, 01→0, 10→0, 11→0
XOR Double-curved shield Rectangle with "=1" Y = A ⊕ B 00→0, 01→1, 10→1, 11→0
XNOR Double-curved with bubble Rectangle with "=1" and bubble Y = (A ⊕ B)' 00→1, 01→0, 10→0, 11→1

How Inversion Modifiers Alter the Base Truth Table

In wire sizing, you apply temperature derating rows to modify a base ampacity value. In digital logic, the equivalent concept is the inversion bubble (or active-low modifier). An inversion bubble on an input or output pin mathematically modifies the base truth table by flipping the binary state of that specific node.

When you place a bubble on an input, you are telling the schematic reader that the pin is active-low. For example, a microcontroller's RESET pin often has a bubble. The base logic might be a simple buffer, but the modifier dictates that a logic 0 (0V) triggers the reset action, while a logic 1 (VCC) allows normal operation.

De Morgan’s Equivalents: The Hidden Modifiers

A common trap for junior engineers is misreading NAND and NOR gates when bubbles are moved. According to De Morgan's Theorems, modifying the base gate with inverted inputs changes the fundamental shape of the gate:

  • NAND (AND gate with output bubble) is electrically identical to an OR gate with inverted inputs.
  • NOR (OR gate with output bubble) is electrically identical to an AND gate with inverted inputs.

Rule of thumb: If you are tracing a schematic and see an OR shape with bubbles on the inputs, do not read it as an OR gate. Read it as a NAND gate. The physical silicon inside a 74HC00 chip doesn't care which symbol you draw; it only cares about the transistor network. Drawing the correct De Morgan equivalent symbol makes the logical intent (e.g., "enable this when both inputs are low") immediately obvious to the person debugging the board.

Decision Path: Choosing the Right Symbol Standard

Which symbol column applies to your installation? The choice is rarely about personal preference; it is dictated by your target manufacturing region, your EDA software defaults, and your industry. Use this decision tree to lock in your schematic library standard.

Table 2: Symbol Standard Decision Matrix
If your project context is... Then choose this standard... Why?
Discrete PCB design in North America (Altium, KiCad, Eagle) ANSI/IEEE 91 (Distinctive Shapes) Default component libraries use these shapes; board house engineers expect them.
Industrial PLC programming or electrical cabinet wiring (EPLAN) IEC 60617 (Rectangular) Mandated by European norms; integrates with ladder logic and function block diagrams.
Military or Aerospace schematics (US DoD contracts) ANSI/IEEE 91 (with MIL-STD-806 extensions) Strict compliance required for legacy MIL-STD documentation and AS9100 audits.
FPGA/ASIC RTL design (Verilog/VHDL synthesis) ANSI/IEEE 91 Synthesis tools (Vivado, Quartus) map RTL directly to ANSI-style schematic viewers.
The Concrete Pick: If you are a hobbyist, student, or commercial hardware designer working outside of heavy European industrial automation, standardize exclusively on ANSI/IEEE 91 distinctive shapes. Mixing IEC rectangular boxes with ANSI D-shapes in the same schematic creates visual friction and increases the time it takes to trace signals during a board bring-up.

What the Truth Table Cannot Tell You (Hardware Realities)

A truth table is a mathematical abstraction. It assumes inputs are perfectly 0V or perfectly 5V, and that the output changes instantaneously. When you move from a textbook to a physical workbench, the truth table fails to warn you about three critical hardware limits. For deeper architectural context, review the MIT Computation Structures coursework on physical digital logic.

1. Voltage Thresholds and Noise Margins

A truth table says "1" means HIGH. But what voltage is a "1"? If you are using a Texas Instruments 74HC series chip powered at 4.5V, the datasheet specifies a minimum $V_{IH}$ (Input High Voltage) of 3.15V. If your microcontroller outputs a 3.3V HIGH signal, it will work. But if your signal sags to 2.8V due to a long, un-terminated trace, the gate will read it as an undefined state, potentially causing oscillation or excess current draw. The truth table hides the $V_{IL}$ and $V_{IH}$ thresholds entirely.

2. Propagation Delay ($t_{pd}$)

When inputs A and B change simultaneously on an XOR gate, the truth table shows the output Y changing instantly. In reality, a standard 74HC86 XOR gate has a propagation delay of roughly 14 nanoseconds at 5V. If you are building a high-speed clock divider or a state machine running at 50 MHz (20ns period), that 14ns delay eats up 70% of your timing budget, leading to setup/hold time violations.

3. Fan-Out and Drive Strength

The truth table implies that one output can feed infinite inputs. Physically, a standard 74HC output can source or sink about 25 mA. If you wire that single output to ten different gate inputs, plus an LED indicator, you may exceed the chip's absolute maximum ratings, causing the output voltage to droop below the $V_{IH}$ threshold of the downstream gates. Always check the datasheet's $I_{OL}$ (Output Low Current) and $I_{OH}$ (Output High Current) specs.

Quick-Jump Reference: Most Queried Logic IC Part Numbers

When you are ordering parts for a breadboard prototype or a quick PCB spin, you rarely need custom ASICs. You need standard jellybean logic. Here are the exact part numbers for the most common 2-input logic gates in the 74HC (High-speed CMOS, 2V to 6V operation) family. Prices reflect typical 2026 distributor rates for single-unit DIP-14 or SOIC-14 packages.

Table 3: Standard 74HC Logic Gate IC Quick-Jump Chart
Function Standard Part Number Gates per Package Typical Price (1pc) Common Use Case
Quad 2-Input AND SN74HC08N (DIP) / SN74HC08D (SOIC) 4 $0.45 Address decoding, enable gating.
Quad 2-Input OR SN74HC32N / SN74HC32D 4 $0.45 Combining interrupt signals (wired-OR alternative).
Quad 2-Input NAND SN74HC00N / SN74HC00D 4 $0.40 Universal logic; building flip-flops from scratch.
Hex Inverter (NOT) SN74HC04N / SN74HC04D 6 $0.42 Signal inversion, buffering, crystal oscillator circuits.
Quad 2-Input XOR SN74HC86N / SN74HC86D 4 $0.55 Parity generators, half-adders, phase detectors.
Hex Schmitt-Trigger SN74HC14N / SN74HC14D 6 $0.50 Debouncing mechanical switches, cleaning up noisy edges.

Final Recommendation: Stop second-guessing your schematic symbols. Standardize your EDA libraries on ANSI/IEEE 91 distinctive shapes for all discrete logic work, memorize the De Morgan equivalents for NAND/NOR bubbles, and always verify your $V_{IH}$ thresholds when mixing 3.3V and 5V logic families. The truth table is just the mathematical starting line; the datasheet is where the actual engineering happens.