A binary full adder is a combinational logic circuit that adds three single-bit binary inputs (A, B, and a Carry-In) to produce a two-bit output (Sum and Carry-Out). In a real digital installation, this component changes a system's ability to scale arithmetic beyond a single bit, forming the fundamental building block of every Arithmetic Logic Unit (ALU) and address generator in modern computing. Beginners commonly confuse it with a half adder, which only accepts two inputs (A and B) and lacks the Carry-In pin required to chain multiple stages together for multi-bit math.
The Truth Table and Boolean Logic Equations
Before wiring up discrete gates or programming an FPGA, you need to internalize the input-to-output mapping. The truth table below covers all eight possible states of the three inputs. Notice how the Carry-Out (Cout) triggers whenever at least two of the three inputs are HIGH (1).
| Carry-In (Cin) | Input A | Input B | Sum (Σ) | Carry-Out (Cout) | Decimal Equivalent |
|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 + 0 + 0 = 0 |
| 0 | 0 | 1 | 1 | 0 | 0 + 0 + 1 = 1 |
| 0 | 1 | 0 | 1 | 0 | 0 + 1 + 0 = 1 |
| 0 | 1 | 1 | 0 | 1 | 0 + 1 + 1 = 2 |
| 1 | 0 | 0 | 1 | 0 | 1 + 0 + 0 = 1 |
| 1 | 0 | 1 | 0 | 1 | 1 + 0 + 1 = 2 |
| 1 | 1 | 0 | 0 | 1 | 1 + 1 + 0 = 2 |
| 1 | 1 | 1 | 1 | 1 | 1 + 1 + 1 = 3 |
Translating this table into hardware requires specific Boolean equations. The Sum output is simply an odd-parity function, achievable with cascaded XOR gates:
The Carry-Out is slightly more complex, triggering when A and B are both high, or when Cin is high and the A⊕B result is high:
Implementing this with discrete 7400-series logic requires two XOR gates, two AND gates, and one OR gate. For a detailed breakdown of gate-level schematics, the All About Circuits digital textbook provides excellent step-by-step derivations.
Worked Numeric Example: Cascading for Multi-Bit Math
To see why the Carry-In pin is non-negotiable, let us add two 4-bit binary numbers: 1011 (decimal 11) and 0111 (decimal 7). We chain four full adders together, feeding the Cout of each stage into the Cin of the next. This configuration is known as a Ripple Carry Adder.
- Bit 0 (LSB): A=1, B=1, Cin=0. Sum = 1⊕1⊕0 = 0. Cout = 1.
- Bit 1: A=1, B=1, Cin=1 (from Bit 0). Sum = 1⊕1⊕1 = 1. Cout = 1.
- Bit 2: A=0, B=1, Cin=1 (from Bit 1). Sum = 0⊕1⊕1 = 0. Cout = 1.
- Bit 3 (MSB): A=1, B=0, Cin=1 (from Bit 2). Sum = 1⊕0⊕1 = 0. Cout = 1.
Reading the final Carry-Out and the Sum bits from MSB to LSB, we get 10010, which is decimal 18. The math checks out (11 + 7 = 18).
Where You Meet This in Practice: Standard ICs and FPGA Primitives
On the bench or in a production schematic, you rarely build full adders from discrete NAND or XOR gates. You use dedicated integrated circuits or hardware primitives optimized for carry propagation.
| Part Number / Primitive | Logic Family | Architecture | Typical Propagation Delay | Best Application |
|---|---|---|---|---|
| SN74LS283 | TTL (Low-Power Schottky) | 4-Bit with Fast Carry Lookahead | ~22 ns | Breadboard prototyping, retro CPU builds |
| CD4008B / HEF4008B | CMOS (4000-series) | 4-Bit Ripple Carry | ~120 ns (at 5V) | Battery-powered logic, wide VCC (3V-15V) |
| Xilinx CARRY4 | FPGA (7-Series / UltraScale) | Dedicated Slice Carry Chain | < 1 ns per stage | High-speed DSP, modern ALU synthesis |
The SN74LS283 is a staple in digital logic labs. Unlike a basic ripple carry design, it uses internal carry-lookahead logic to generate the carry bits in parallel, drastically reducing the propagation delay from the LSB to the MSB. You can cascade two 74LS283 chips to create an 8-bit adder by tying the C4 (Carry-Out) pin of the lower nibble directly to the C0 (Carry-In) pin of the upper nibble.
In modern FPGA design (like Xilinx/AMD or Intel/Altera architectures), synthesis tools do not map adders to standard Look-Up Tables (LUTs). Instead, they route the math through dedicated silicon called CARRY4 primitives. These are hardwired multiplexer chains physically located between the LUTs and flip-flops in a logic slice, allowing 32-bit additions to complete in a single clock cycle at 200+ MHz.
Bench Debugging and Common Confusions
When prototyping adder circuits, a few specific hardware gotchas will ruin your afternoon if you aren't expecting them.
The CMOS Floating Input Trap
If you are using a CMOS 4000-series adder like the CD4008B, never leave the Carry-In (Cin) pin of the first stage unconnected. Beginners often assume an unconnected pin defaults to LOW (0). In TTL logic, this is sometimes true due to internal pull-ups. In CMOS, an unconnected pin acts as a high-impedance antenna. It will pick up 50/60Hz mains noise from your body and the bench, causing the internal transistors to oscillate wildly. This results in erratic Sum outputs and excessive quiescent current (IDDQ), making the chip physically hot to the touch. Always tie unused Cin pins directly to GND via a hard wire.
Half Adder vs. Full Adder
A half adder can only add two bits (A and B). It generates a Sum and a Carry-Out, but it has no Carry-In. Therefore, a half adder can only ever be used for the very first stage (the LSB) of a multi-bit adder. Every subsequent bit requires a full adder to absorb the carry from the previous stage. If your multi-bit circuit is consistently off by exactly 1 or 2 in the higher bits, check that you haven't accidentally wired half-adder logic (missing the Cin XOR gate) into the upper stages.
Frequently Asked Questions
Q: Can I use a full adder to subtract binary numbers?
A: Yes. By inverting the B inputs (using NOT gates) and setting the initial Carry-In to HIGH (1), the full adder circuit performs two's complement subtraction (A - B). This is exactly how the 74LS283 is wired inside a basic ALU to handle both addition and subtraction.
Q: What is the fan-out limit on the Carry-Out pin?
A: In standard 74LS TTL, the fan-out is typically 10 LS-TTL loads. However, in a ripple carry chain, the Cout only drives the Cin of the next adder stage (a load of 1). Fan-out only becomes an issue if you try to tap the intermediate carry signals to drive multiple external indicator LEDs or logic gates without using a buffer.
Q: Why do FPGAs use dedicated carry chains instead of LUTs?
A: Routing carry signals through standard programmable interconnects introduces variable, unpredictable delays that limit maximum clock frequency (Fmax). Dedicated carry chains use fixed, ultra-short silicon pathways between adjacent logic slices, ensuring deterministic timing and allowing the compiler to easily meet timing closure on 32-bit or 64-bit math operations.
