A standard truth table for logic gates maps binary inputs (0 and 1) to a binary output based on Boolean algebra. But on the workbench, a logic "1" is not an abstract concept—it is a specific physical voltage. For a 5V 74HC CMOS gate, a logic HIGH output is typically 4.9V under light load, while a 3.3V 74LVC gate outputs roughly 3.2V. If you are interfacing discrete logic ICs with microcontrollers, relying solely on 1s and 0s will lead to fried GPIO pins or unstable reads. This reference bridges the gap between ideal Boolean truth tables and the physical voltage levels, logic families, and loading constraints you must account for in real circuits.
The Master Truth Table for Logic Gates (Boolean & Voltage States)
The table below merges the theoretical Boolean states with the guaranteed electrical output voltages for the two most common logic families used in modern DIY and prototyping: 5V CMOS (74HC series) and 3.3V CMOS (74LVC series). Voltage thresholds are defined per Texas Instruments JEDEC-compliant datasheets and IEEE Std 91A-1991 graphic symbols.
| Gate Type | Boolean Rule | Input A | Input B | Ideal Out | 74HC (5V) $V_{out}$ | 74LVC (3.3V) $V_{out}$ |
|---|---|---|---|---|---|---|
| AND | A · B | 1 | 1 | 1 | 4.90V | 3.20V |
| AND | A · B | 1 / 0 | 0 / 1 | 0 | 0.10V | 0.05V |
| OR | A + B | 1 | 0 / 1 | 1 | 4.90V | 3.20V |
| OR | A + B | 0 | 0 | 0 | 0.10V | 0.05V |
| XOR | A ⊕ B | 1 | 0 | 1 | 4.90V | 3.20V |
| XOR | A ⊕ B | 1 | 1 | 0 | 0.10V | 0.05V |
| NAND | $\overline{A \cdot B}$ | 1 | 1 | 0 | 0.10V | 0.05V |
| NAND | $\overline{A \cdot B}$ | 0 | 0 / 1 | 1 | 4.90V | 3.20V |
How to read this table: The "Ideal Out" column represents the pure Boolean state. The voltage columns represent the guaranteed minimum $V_{OH}$ (Output High Voltage) and maximum $V_{OL}$ (Output Low Voltage) assuming a standard 2mA output current load. These values assume an ambient temperature rating of 25°C (77°F). If your installation operates in an enclosure at 85°C, expect the guaranteed $V_{OH}$ to drop by approximately 0.1V to 0.15V due to increased silicon on-resistance, and $V_{OL}$ to rise slightly. Bookmark the row IDs (e.g., #gate-and) for quick reference during bench testing.
Which Logic Family Column Applies to Your Installation?
Choosing the wrong column from the truth table above is the most common cause of destroyed microcontrollers in mixed-signal projects. The column you must use depends entirely on your microcontroller's VCC rail and its absolute maximum GPIO ratings.
For a comprehensive breakdown of digital logic families and their historical evolution, the All About Circuits digital logic textbook provides excellent foundational theory, but always defer to the specific manufacturer datasheet for exact threshold voltages.
How Derating Rows Modify the Base Value
In power electronics, derating usually refers to thermal limits. In logic ICs, "derating" manifests as fan-out loading and capacitive derating. The truth table voltages above assume a minimal 2mA load. However, every logic gate input presents a small parasitic capacitance (typically 3pF to 10pF per pin).
If your 74HC gate output is wired to drive 10 subsequent gate inputs (a fan-out of 10), the total capacitive load increases to roughly 50pF. Datasheet derating curves show how this capacitive loading modifies the base value: the propagation delay ($t_{pd}$) will stretch from a baseline of 10ns up to 25ns or more. Furthermore, if you are sourcing higher current (e.g., 6mA to drive an LED indicator), the $V_{OH}$ will sag from 4.9V down toward 4.4V. Always check the $I_{OH}$ (Output High Current) derating graphs in the SN74LVC1G08 datasheet to ensure your loaded voltage remains above the receiving gate's $V_{IH}$ (Input High Voltage) threshold.
What the Truth Table Cannot Tell You: Timing and Analog Failures
A static truth table for logic gates is a snapshot of steady-state DC conditions. It is entirely blind to time-domain behavior and analog transition regions. When debugging a circuit that "should work according to the truth table" but is outputting garbage data, the failure is almost always found in one of these three blind spots.
1. Propagation Delay and Race Conditions
When Input A transitions from 0 to 1, the output does not change instantaneously. A standard 74HC gate has a propagation delay ($t_{pd}$) of roughly 10ns to 15ns. If you are building a discrete ripple-carry adder or a state machine using multiple gates, the signal takes different physical paths through the ICs. This creates a "race condition" where intermediate, false Boolean states appear on the output for a few nanoseconds before settling to the final truth table value. In high-speed circuits, these glitches can accidentally clock a flip-flop.
2. The Analog Transition Region (Floating Inputs)
The truth table assumes inputs are firmly at 0V or VCC. If you leave a CMOS input pin unconnected (floating), or if your input signal rises too slowly through the threshold region (between $V_{IL}$ and $V_{IH}$), the internal MOSFETs enter their linear region. The gate stops acting as a digital switch and becomes a high-gain analog amplifier. It will amplify thermal noise, oscillate at high frequencies, and cause the IC's quiescent current ($I_{CC}$) to spike from microamps to milliamps, physically heating the chip. Never leave unused logic gate inputs floating; always tie them to VCC or GND via a 10kΩ resistor.
3. Metastability in Sequential Logic
While basic combinational gates (AND, OR) simply resolve to a new state based on inputs, sequential logic elements (like D flip-flops, which are built from these gates) require strict setup and hold times. If the input data changes at the exact nanosecond the clock edge arrives, the flip-flop enters a metastable state. The output may hover at an invalid voltage (e.g., 2.5V on a 5V rail) for an unpredictable amount of time before resolving to a 1 or 0. A truth table cannot predict metastability; resolving it requires proper synchronization chains and strict adherence to timing diagrams, not just Boolean equations.
