The open loop gain of an op amp ($A_{OL}$) is the intrinsic voltage amplification factor of the device when no external feedback network is connected between the output and the inputs. In modern silicon, this number is massive—typically ranging from 100,000 V/V (100 dB) to over 1,000,000 V/V (120 dB) at DC. However, you will almost never use an operational amplifier in a true open-loop configuration for linear signal amplification. Because the gain is so high, even microvolts of differential input voltage will instantly drive the output into saturation against the supply rails.
Instead, the open loop gain of an op amp dictates the accuracy of your closed-loop circuits. It determines your gain error, linearity, and output impedance when you apply negative feedback. If you need reliable, safe default part numbers for your bench: the LM358 (single-supply, ~100 dB $A_{OL}$, ~$0.15/unit) is the standard for low-cost DC applications; the TL072 (JFET input, ~106 dB $A_{OL}$, ~$0.40/unit) is the go-to for audio and low-noise; and the OPA2134 (FET input, ~120 dB $A_{OL}$, ~$4.50/unit) is the premium choice for high-precision instrumentation.
The Spec Sheet Reality: Open-Loop Gain vs. Closed-Loop Performance
When reading a datasheet, $A_{OL}$ is usually specified at DC (0 Hz). But as frequency increases, the internal compensation capacitor causes the open-loop gain to roll off at -20 dB/decade. This creates the Gain-Bandwidth Product (GBWP). The higher your closed-loop gain, the less bandwidth you have available before the finite $A_{OL}$ introduces significant phase shift and gain error.
The gain error in a closed-loop non-inverting amplifier is calculated as: Error = 1 / ($A_{OL}$ × β), where β is the feedback factor. If your $A_{OL}$ is 100,000 and you design for a closed-loop gain of 100 (β = 0.01), your theoretical gain error is 0.1%. If you push the frequency up and $A_{OL}$ drops to 1,000, that error balloons to 10%.
| Part Number | Open Loop Gain ($A_{OL}$) | GBWP | Slew Rate | Supply Range | Typ. 2026 Price |
|---|---|---|---|---|---|
| LM358 (TI/ON Semi) | 100,000 V/V (100 dB) | 1 MHz | 0.3 V/µs | 3V to 32V (Single/Dual) | $0.12 - $0.18 |
| TL072 (TI) | 200,000 V/V (106 dB) | 3 MHz | 13 V/µs | ±5V to ±15V (Dual) | $0.35 - $0.45 |
| OPA2134 (TI/Burr-Brown) | 1,000,000 V/V (120 dB) | 8 MHz | 20 V/µs | ±2.5V to ±18V (Dual) | $4.20 - $4.80 |
| MCP6002 (Microchip) | 112,000 V/V (101 dB) | 1 MHz | 0.6 V/µs | 1.8V to 6.0V (Single) | $0.25 - $0.32 |
For a deeper look into how internal compensation affects these parameters, the TI Precision Labs Op-Amp series provides excellent bench-level demonstrations of gain roll-off and phase margin.
Pinouts, Biasing, and Operation Regions
To utilize the open loop gain of an op amp effectively, you must correctly bias the inputs and understand the physical pinout. The industry-standard 8-pin DIP/SOIC dual op-amp layout is as follows:
- Pin 1: Offset Null / NC (Not Connected on modern FET parts)
- Pin 2: Inverting Input (-)
- Pin 3: Non-Inverting Input (+)
- Pin 4: V- (GND for single supply, VEE for dual supply)
- Pin 5: Offset Null / NC
- Pin 6: Output
- Pin 7: V+ (VCC)
- Pin 8: NC
Because the open loop gain is so immense, the op-amp operates in one of three distinct regions depending on the differential voltage ($V_{diff}$) between Pin 3 and Pin 2.
| Operation Region | Differential Input ($V_{diff}$) | Output Voltage State | Output Current Limit | Primary Use Case |
|---|---|---|---|---|
| Linear (Active) | -0.1 mV to +0.1 mV | $V_{EE} + 1.5V$ to $V_{CC} - 1.5V$ (Standard parts) | ±20 mA to ±40 mA | Closed-loop amplifiers, active filters |
| Positive Saturation | > +0.2 mV | Clamped near $V_{CC}$ (or $V_{CC}-1.5V$) | Short-circuit protected (~25 mA) | Comparators, Schmitt triggers |
| Negative Saturation | < -0.2 mV | Clamped near $V_{EE}$ (or $V_{EE}+1.5V$) | Short-circuit protected (~25 mA) | Comparators, logic level shifting |
Practical Application: Designing a Stable Non-Inverting Amplifier
Let's harness the open loop gain of an op amp to build a precision non-inverting amplifier with a closed-loop gain of 10 V/V (20 dB). We will use the TL072 for its low noise and high $A_{OL}$.
Target Equation: $A_{CL} = 1 + (R_f / R_g)$
Component Selection: To get a gain of 10, we need $R_f / R_g = 9$. We choose $R_f = 90 k\Omega$ and $R_g = 10 k\Omega$. We use 1% metal film resistors to keep passive tolerance errors below the op-amp's intrinsic gain error.
Complete Circuit Bill of Materials & Wiring
- Power Bypassing: Place a 100 nF (0.1 µF) MLCC ceramic capacitor and a 10 µF electrolytic capacitor physically within 5 mm of Pin 7 (VCC to GND) and Pin 4 (VEE to GND). This prevents high-frequency oscillation caused by power rail inductance.
- Feedback Network: Connect the 90 kΩ resistor ($R_f$) from Pin 6 (Output) to Pin 2 (Inverting Input).
- Ground Reference: Connect the 10 kΩ resistor ($R_g$) from Pin 2 (Inverting Input) to Circuit Ground.
- Input Coupling: Route your AC signal through a 1 µF film capacitor to Pin 3 (Non-Inverting Input) to block DC offsets. Add a 100 kΩ pull-down resistor from Pin 3 to Ground to provide a DC return path for the JFET input bias current.
- Output Isolation: Place a 47 Ω resistor in series with Pin 6 before the output jack. This isolates the op-amp's output stage from capacitive loads (like long cables), preventing phase-margin degradation and ringing.
With the TL072's $A_{OL}$ of 200,000 V/V and our feedback factor β of 0.1 (since $R_g / (R_f + R_g) = 10k / 100k$), the theoretical gain error is $1 / (200,000 × 0.1) = 0.005\%$. The 1% tolerance of your physical resistors will dominate the error budget, proving that high open-loop gain successfully removes the amplifier itself as a source of inaccuracy.
Failure Modes and Bench Testing with a Multimeter
Op-amps rarely fail gracefully. The most common failure mode is Electrical Overstress (EOS), where a voltage spike exceeds the absolute maximum supply ratings or the input differential voltage limit, melting the input stage junctions. ESD (Electrostatic Discharge) can also punch through the gate oxide on CMOS/FET inputs, causing massive input bias current leaks.
If your circuit is saturating unexpectedly or outputting noise, use your digital multimeter (DMM) to diagnose the IC. For authoritative guidelines on handling and testing semiconductor limits, refer to the Analog Devices Op-Amp Basics library.
DMM Diagnostic Sequence
- De-energize and Discharge: Remove power from the breadboard/PCB. Short the power rails with a 1 kΩ resistor to discharge bypass capacitors.
- Input Stage Diode Test (BJT Parts like LM358): Set DMM to Diode Test. Place the red probe on Pin 2 (Inverting) and black on Pin 4 (V-). You should read ~0.6V to 0.7V (the base-emitter junction). Reverse probes; it should read 'OL' (Open Loop). Repeat for Pin 3. Note: JFET/CMOS parts like TL072 or MCP6002 will read 'OL' in both directions because they lack these protection diodes.
- Output Stage Check: Set DMM to resistance (Ω). Measure between Pin 6 (Output) and Pin 4 (V-), then Pin 6 and Pin 7 (V+). You should read high resistance (typically >10 kΩ). If you read a dead short (< 5 Ω), the output pull-up or pull-down transistor has blown due to a short-circuit load.
- The "Virtual Short" Powered Test: Re-apply power to a closed-loop circuit (like the non-inverting amp above). Set DMM to DC mV. Measure directly between Pin 3 and Pin 2. Because negative feedback forces the inputs to match, you should read less than 1 mV. If you read > 10 mV while the output is not saturated, the op-amp's internal differential pair is damaged, or the feedback loop is broken.
By understanding the open loop gain of an op amp not just as a datasheet curiosity, but as the foundational parameter that enables precision feedback, you can select the right silicon, design stable networks, and confidently troubleshoot failures on the bench.
