When you trace the analog front-end of a mixed-signal PCB or the output stage of an audio DAC, you will inevitably encounter the Sallen-Key topology. It is the undisputed workhorse of active analog filtering. Understanding how to read, design, and troubleshoot these specific circuit board schematics bridges the gap between abstract transfer functions and physical, working hardware.
This guide breaks down the unity-gain Sallen-Key low-pass filter. We will map the nodes, select real-world E12 series components for a 1 kHz Butterworth response, analyze extreme failure modes, and walk through a bench-testing protocol.
Sallen-Key Topology Description and Node Labels
The unity-gain Sallen-Key low-pass filter uses a single operational amplifier configured as a voltage follower (buffer), preceded by a two-stage RC network with a clever feedback loop. To read this topology on circuit board schematics, you must identify four critical nodes:
- Node $V_{in}$: The AC signal input, typically AC-coupled via a series capacitor to block upstream DC offsets.
- Node A (R1/R2 Junction): The intermediate node between the two series resistors. This is where the primary feedback capacitor (C1) injects signal from the output to shape the Q-factor.
- Node B (Non-Inverting Input): The junction of R2 and the shunt capacitor (C2). This node directly drives the op-amp's high-impedance input.
- Node $V_{out}$: The op-amp output, which is tied directly back to the inverting input (unity gain) and routes to C1.
You will often see the MFB topology on circuit board schematics for high-Q bandpass filters. However, for low-pass applications with a Q < 3, the Sallen-Key topology wins. It requires lower op-amp gain-bandwidth product (GBWP), is less sensitive to capacitor tolerance variations, and offers a non-inverting output. MFB is strictly preferred when you need signal inversion or are designing for very high Q-factors where Sallen-Key component spreads become impractical.
Design Walkthrough: Picking Real Component Values
Let's design a 1 kHz low-pass filter with a Butterworth response (maximally flat passband, Q = 0.707). For a unity-gain Sallen-Key Butterworth filter, the standard design equations dictate that $R1 = R2$ and $C1 = 2 \times C2$.
We start by selecting a standard resistor value to keep impedance low enough to minimize thermal noise, but high enough to avoid overloading the op-amp. Let's choose R1 = R2 = 10 kΩ.
Using the cutoff frequency formula $f_c = \frac{1}{2\pi R \sqrt{C1 \cdot C2}}$ and substituting $C1 = 2C2$:
$C2 = \frac{1}{2\pi \cdot R \cdot f_c \cdot \sqrt{2}}$
Plugging in 10 kΩ and 1000 Hz yields a theoretical C2 of 11.25 nF. Since we must use standard real-world components, we select the closest E12 values:
- C2 = 10 nF (X7R ceramic, 50V rated)
- C1 = 22 nF (X7R ceramic, 50V rated - closest to the theoretical 20 nF)
Recalculating the actual cutoff frequency with these real values: $f_c = \frac{1}{2\pi \cdot 10000 \cdot \sqrt{22\times10^{-9} \cdot 10\times10^{-9}}} \approx 1073 \text{ Hz}$. This 7% deviation is entirely acceptable for standard audio and sensor conditioning. For the op-amp, avoid the LM358 if this is an audio circuit; its class-B output stage introduces crossover distortion near 0V. Use a TL072 or OPA2134 for clean, low-noise performance.
Behavior Table: Component Variations and Failure Modes
Reading circuit board schematics is only half the battle; you must understand how the circuit behaves when physical components degrade or fail. The table below contrasts normal parameter drift with catastrophic open/short failures.
| Component | Nominal Role | If Value Increases (Drift) | Extreme Failure: OPEN | Extreme Failure: SHORT |
|---|---|---|---|---|
| R1 (10k) | Sets input impedance and time constant with C1. | Cutoff frequency drops; passband attenuation increases slightly. | Signal path broken. $V_{out}$ drops to 0V (or floats to mid-rail if biased). | C1 is now tied directly to $V_{in}$. Circuit becomes a 1st-order filter (C2/R2) losing -40dB/decade roll-off. |
| R2 (10k) | Isolates Node A from Node B; sets time constant with C2. | Cutoff frequency drops; Q-factor decreases (response becomes overdamped). | Node B floats. Op-amp input bias current charges parasitic capacitance, $V_{out}$ rails to VCC or VEE. | Node A ties to Node B. C1 and C2 are effectively paralleled. Filter becomes 1st-order. |
| C1 (22nF) | Provides positive feedback to shape the Q-factor (Butterworth peaking). | Q-factor drops; transition band becomes sluggish and overdamped. | Feedback loop broken. Circuit degrades to a passive 2nd-order RC filter followed by a buffer. Roll-off softens. | Node A shorts to $V_{out}$. Op-amp output drives directly into the R1/R2 resistive divider. High current draw, potential thermal shutdown. |
| C2 (10nF) | Shunts high frequencies to ground at the op-amp input. | Cutoff frequency drops; high-frequency attenuation improves. | Node B floats to DC rail. $V_{out}$ saturates. No AC signal passes. | Node B is hard-grounded. Op-amp non-inverting input is at 0V. $V_{out}$ sits at 0V (or virtual ground reference). |
Step-by-Step Breadboard Testing Protocol
Translating circuit board schematics to a physical breadboard introduces parasitic capacitance (typically 2-5 pF per node). While negligible at 1 kHz, these parasitics will destroy a 1 MHz filter design. Here is how to prototype and verify the 1 kHz Sallen-Key filter on the bench.
- Prepare the Power Rails: Insert the TL072 op-amp across the center trench. Connect Pin 8 to +12V and Pin 4 to -12V (or GND for single-supply, with a 5V bias network). Critical: Place a 100 nF MLCC decoupling capacitor directly across the power pins of the op-amp, as close to the IC body as possible.
- Wire the Unity-Gain Feedback: Connect Pin 1 (Output) directly to Pin 2 (Inverting Input) using a short, stiff jumper wire. Keep this loop as tight as possible to prevent high-frequency oscillation.
- Build the RC Network: Insert R1 and R2 in series. Connect C2 from the R2/op-amp junction (Node B) to ground. Connect C1 from the R1/R2 junction (Node A) to the op-amp output (Pin 1).
- Inject the Signal: Connect a function generator to $V_{in}$. Set it to output a 1 Vpp sine wave with a 0V DC offset. Start the frequency sweep at 100 Hz.
- Probe and Verify: Connect your oscilloscope using a 10x probe. Use the probe's ground spring (not the long alligator clip lead) to minimize ground loop inductance, which causes ringing on the scope display. Measure $V_{out}$ amplitude.
- Find the -3dB Point: Increase the generator frequency. At ~1073 Hz, the output amplitude should drop to 0.707 Vpp (-3dB). Continue to 10 kHz; the amplitude should be roughly 0.01 Vpp, confirming the -40dB/decade roll-off characteristic of a 2nd-order filter.
Frequently Asked Questions About Circuit Board Schematics
How do I differentiate analog and digital ground on circuit board schematics?
On mixed-signal circuit board schematics, you will see distinct symbols for Analog Ground (AGND) and Digital Ground (DGND). AGND is typically represented by a standard earth ground or signal ground symbol, while DGND often uses a triangular or hollow symbol. In the schematic, they appear isolated to prevent noisy digital return currents from modulating the sensitive analog reference. However, in the physical PCB layout, they must be tied together at exactly one point (a "star ground")—usually directly beneath the ADC or DAC chip—to maintain a single equipotential reference plane and prevent ground loops.
What is the standard grid size for drawing circuit board schematics?
The universal standard for schematic capture in tools like Altium, KiCad, and OrCAD is a 100 mil (0.1 inch) grid. Component pins and wire endpoints must snap to this grid. If you draw a wire that ends at 95 mils, the design rule check (DRC) will flag a "broken net" error because the electrical connection is not mathematically closed. Always keep your schematic grid locked to 100 mils for wiring, and use a 50 mil or 25 mil grid only when placing text or drawing non-electrical graphical boxes.
Why do circuit board schematics use different resistor symbols?
You will encounter two primary resistor symbols on circuit board schematics: the US standard zig-zag line and the IEC (International Electrotechnical Commission) standard rectangular box. The choice is purely regional and historical; electrically, they are identical. However, modern EDA tools allow you to switch between IEEE (zig-zag) and IEC (rectangle) standards globally. The critical detail is not the shape, but the annotations: a diagonal arrow through the symbol indicates a variable resistor (potentiometer), while a box with an arrow pointing inward denotes a light-dependent resistor (LDR) or other sensor.
