RGMII voltage translation from 0.9V to 3.3V is the process of shifting the logic levels of a Reduced Gigabit Media Independent Interface between a low-voltage SoC/FPGA (0.9V) and a standard Ethernet PHY (3.3V) while preserving the strict sub-nanosecond timing and skew margins required for 125 MHz DDR data transfer. In a real circuit, this translation changes your power delivery network—requiring clean, isolated 0.9V and 3.3V rails—and forces strict impedance-controlled PCB routing. Beginners commonly confuse this with RMII (which runs at 50 MHz single-data-rate and is far more forgiving) or basic I2C/GPIO level shifting (where propagation delay is irrelevant and open-drain architectures dominate).
The 125 MHz DDR Timing Budget (Numeric Example)
To understand why you cannot use a standard level shifter for this task, you must calculate the timing budget. RGMII clocks at 125 MHz for Gigabit Ethernet, yielding an 8 ns period. Because it uses DDR (Double Data Rate), data transitions on both the rising and falling edges of the clock.
Let us run a worked numeric example for a typical MAC-to-PHY interface using a PHY like the Microchip KSZ9031. The PHY requires a minimum setup and hold time of roughly 1.2 ns.
- SoC Output Skew: 0.3 ns (variation between data pins and the clock pin)
- Level Shifter Channel-to-Channel Skew: 0.5 ns (using a matched AVC-family translator)
- PCB Trace Skew: 0.2 ns (assuming 5-mil length matching per byte lane)
- Total Timing Uncertainty: 1.0 ns
Subtracting the 1.0 ns uncertainty and the 1.2 ns PHY setup/hold requirement from our 4.0 ns data eye leaves exactly 1.8 ns of timing margin. If you substitute the matched translator with a basic MOSFET-based bidirectional shifter (which often exhibits 2.0 ns to 3.0 ns of channel-to-channel skew and 5 ns+ propagation delay), your total uncertainty exceeds the 4.0 ns data eye. The result is intermittent packet loss, CRC errors, and a link that drops under thermal load.
Where You Meet This in Practice
You will encounter the 0.9V to 3.3V RGMII translation requirement primarily in modern edge AI accelerators, advanced FPGAs (like Xilinx Zynq UltraScale+), and high-end mobile SoCs. To manage Thermal Design Power (TDP) and prevent silicon degradation on advanced FinFET nodes (5nm/7nm), manufacturers push specific IO bank voltages down to 0.9V or even 0.8V.
This is not a simple logic high/low translation; it is a high-speed signal integrity challenge. The translator IC must source and sink enough current to charge and discharge the PCB trace capacitance in under 1 ns, ensuring the square waves do not round off into sine waves before reaching the PHY.
Decision Tree: Picking the Right Translator IC
Choosing the wrong logic family will brick your Ethernet link. Use this decision matrix to select your component.
| Criteria | Standard Auto-Direction (e.g., TXS0108E) | LVC/AUP Family (e.g., 74LVC8T245) | AVC Family (e.g., SN74AVC16T245) |
|---|---|---|---|
| VccA Support (0.9V) | Fails (Min 1.2V) | Fails (Min 1.2V) | Passes (Supports 0.8V to 3.6V) |
| Propagation Delay ($t_{pd}$) | ~6.0 ns (Too slow) | ~2.5 ns (Marginal) | ~2.2 ns (Matched and fast) |
| Channel-to-Channel Skew | ~3.0 ns (Fatal) | ~0.5 ns (Good) | ~0.4 ns (Excellent) |
| Drive Strength at 3.3V | Weak (Resistor-based) | Strong (24mA) | Strong (Dynamic drive) |
| Verdict for 125MHz RGMII | Reject | Reject (VccA too low) | SELECT |
PCB Layout Rules for 0.9V to 3.3V RGMII
Even with the correct IC, poor PCB layout will introduce skew that the translator cannot fix. Follow these strict layout rules:
- Impedance Control: Route all RGMII traces as 50-ohm single-ended microstrip or stripline. Do not route them as 100-ohm differential pairs; RGMII is single-ended.
- Length Matching: Match the trace lengths of TXD[3:0] to TX_CTL and TX_CLK within 5 mils. Do the same for the RX byte lane. The clock trace does not need to match the data traces in length, but the data traces must match each other.
- The 1.5 ns Clock Delay: The RGMII specification requires the TX clock to be delayed by 1.5 ns to 2.0 ns relative to the data at the PHY. If your MAC and PHY do not support internal delay (ID) modes, you must add this delay via PCB trace routing. At a typical FR4 propagation velocity of ~150 ps/inch, a 1.5 ns delay requires roughly 10 to 12 inches of extra serpentine trace on the TX_CLK line.
- Dual-Rail Decoupling: The AVC translator has two Vcc pins (VccA and VccB). Place a 100 nF X7R ceramic capacitor within 2 mm of every Vcc pin, routed directly to the adjacent ground via. Do not share vias between the 0.9V and 3.3V decoupling return paths.
FAQ: RGMII Translation Edge Cases
Can I just use series resistors to drop 3.3V down to 0.9V?
No. A resistor divider will destroy the edge rates required for 125 MHz DDR. Furthermore, RGMII is bidirectional for some management signals, and the 0.9V SoC IOs lack the drive strength to push current back through a passive divider to reach the 3.3V PHY threshold. You must use an active, dual-supply buffer.
Do I need to translate the MDIO and MDC lines with the same high-speed IC?
MDIO (Management Data Input/Output) and MDC (Management Data Clock) run at a maximum of 2.5 MHz to 5 MHz. While you can route them through the SN74AVC16T245 if you have spare channels, it is perfectly acceptable to use a standard, low-cost shifter like the TXS0108E or even a simple discrete MOSFET translator for these two specific pins to save board space and BOM cost.
What happens if my 0.9V rail has 50mV of ripple?
At 0.9V nominal, a 50mV ripple represents a >5% variance. Because the AVC translator's switching threshold on the A-side is roughly $0.5 imes VccA$ (approx 450mV), severe ripple can cause false triggering or jitter on the clock edge. Ensure your 0.9V PMIC output has less than 15mV of peak-to-peak ripple and use a localized 10 uF bulk capacitor near the translator IC.
