The direct answer for engineers and hobbyists designing custom capacitive sensors: the formula for capacitance of parallel plate capacitor is C = (ε₀ · εᵣ · A) / d. While textbooks treat this as abstract physics, on the workbench, this formula is the foundational design constraint for PCB touch pads, proximity sensors, and custom timing elements. If you miscalculate the plate area (A) or dielectric thickness (d), your readout circuit will either fail to oscillate or drown in parasitic noise.
In this guide, we will use the parallel plate formula to design a physical 100 pF capacitive sensor using copper tape and Kapton, then configure a CMOS 555 timer astable topology to read it. We will cover the exact component values, failure modes at the physical extremes, and a step-by-step breadboard verification process.
The Physics: Calculating Your PCB Capacitor
To build a custom parallel plate capacitor, you must manipulate four variables. The governing equation is:
C = (ε₀ · εᵣ · A) / d
Where:
C = Capacitance in Farads
ε₀ = Vacuum permittivity (8.854 × 10⁻¹² F/m)
εᵣ = Relative permittivity (dielectric constant) of the material
A = Overlapping area of the plates in square meters
d = Distance (thickness of dielectric) between plates in meters
Design Walkthrough: Targeting 100 pF
Let's design a sensor with a target capacitance of 100 pF (100 × 10⁻¹² F) using copper tape and 2-mil Kapton tape as the dielectric.
- Target C: 100 × 10⁻¹² F
- Dielectric (d): 0.0508 mm (5.08 × 10⁻⁵ m)
- Dielectric Constant (εᵣ): 3.4 (Kapton)
Rearranging the formula to solve for Area (A):
A = (C · d) / (ε₀ · εᵣ)
A = (100 × 10⁻¹² · 5.08 × 10⁻⁵) / (8.854 × 10⁻¹² · 3.4)
A = 5.08 × 10⁻¹⁵ / 3.01 × 10⁻¹¹
A ≈ 1.68 × 10⁻⁴ m² (or 1.68 cm²)
To achieve this, you need two copper plates measuring exactly 1.3 cm × 1.3 cm, separated by a single layer of 2-mil Kapton tape.
Readout Topology: TLC555 Astable Multivibrator
Converting capacitance to a measurable signal requires an oscillator topology. We will use an astable multivibrator. However, you must not use a standard bipolar NE555 for this. The NE555 has an input bias current of ~100 nA on the threshold pins, which will charge a 100 pF capacitor in microseconds, completely breaking the timing equation. Instead, we use the TLC555 (CMOS variant), which has a pA-level bias current.
Topology Description & Node Labels
The TLC555 astable configuration uses two resistors and our custom parallel plate capacitor (C1).
- VCC (Pin 8): Tied to +5V DC.
- GND (Pin 1): Tied to 0V system ground.
- DISCH (Pin 7): Connected to VCC through Resistor R1 (10 kΩ).
- THRES (Pin 6) & TRIG (Pin 2): Tied together. Connected to DISCH (Pin 7) through Resistor R2 (140 kΩ).
- Custom Capacitor (C1): Connected between the THRES/TRIG node and GND. (This is our 1.3cm x 1.3cm Kapton parallel plate).
- OUT (Pin 3): Square wave output to microcontroller or frequency counter.
Component Value Verification
The frequency formula for a 555 astable is f = 1.44 / ((R1 + 2·R2) · C).
With R1 = 10k, R2 = 140k, and C = 100pF:
f = 1.44 / ((10,000 + 280,000) · 100 × 10⁻¹²)
f = 1.44 / (290,000 · 10⁻¹⁰) = 49,655 Hz (approx. 49.7 kHz).
This yields a clean, easily measurable square wave with a 51.7% duty cycle.
Behavior Matrix: Physical Changes vs. Circuit Output
When using a parallel plate capacitor as a sensor, physical environmental changes alter the variables in the capacitance formula, which directly shifts the TLC555 output frequency. Here is how the topology responds to physical manipulation.
| Physical Element Changed | Effect on Formula Variable | Capacitance (C) Change | TLC555 Output Frequency |
|---|---|---|---|
| Increase Plate Area (A) | Larger overlapping surface | Increases | Decreases |
| Compress Dielectric (Decrease d) | Plates pushed closer together | Increases | Decreases |
| Introduce Moisture / Water | Increases εᵣ (Water εᵣ ≈ 80) | Increases drastically | Decreases drastically |
| Slide Plates Laterally (Decrease A) | Reduces overlapping surface | Decreases | Increases |
Decision Tree: Choosing the Right Readout Topology
Why choose the TLC555 astable over alternatives like an LC tank or a dedicated capacitance-to-digital converter (CDC)? The choice is strictly dictated by the calculated capacitance value and your budget. Use this decision path to finalize your readout IC.
| Calculated Capacitance (C) | Recommended Topology / IC | Why This Wins |
|---|---|---|
| < 5 pF | LC Colpitts Oscillator or FDC2214 CDC | Stray breadboard capacitance (2-5pF) will overwhelm a 555 timer at this range. LC tanks or dedicated I2C CDCs reject parasitics better. |
| 10 pF to 10 nF | CMOS 555 (TLC555 / LMC555) Astable | Default Pick. High input impedance prevents bias-current charging errors. Cheap ($0.50), requires no SPI/I2C code, outputs direct square wave. |
| > 10 nF | Bipolar NE555 or MCU GPIO RC-Charge | At high capacitance, the TLC555's low drive current struggles to discharge the cap quickly. A standard NE555 (200mA sink) or direct MCU pin charging is more robust. |
Final Decision: Because our Kapton parallel plate design yields exactly 100 pF, the decision tree mandates the TLC555 CMOS astable topology. It avoids the parasitic traps of the sub-5pF range while remaining well within the CMOS IC's optimal timing window.
Breadboard Prototyping: Step-by-Step Verification
Before etching a PCB, you must validate the formula's real-world output. Breadboards introduce ~3 pF of stray capacitance per row, which is acceptable for our 100 pF target but requires careful layout. For deeper theory on parasitic capacitance in prototyping environments, refer to All About Circuits' capacitance guidelines.
- Prepare the Plates: Cut two exact 1.3 cm × 1.3 cm squares of copper foil tape. Solder a 24 AWG solid-core pigtail to the non-adhesive side of each square before assembling.
- Apply the Dielectric: Stick a single layer of 2-mil Kapton tape over the adhesive side of the bottom copper plate. Ensure no air bubbles, which would locally increase 'd' and reduce capacitance.
- Assemble the Stack: Press the top copper plate onto the Kapton layer. The adhesive side of the top plate should face up. Ensure the edges do not overlap or short out.
- Wire the TLC555: Insert the TLC555 into the breadboard. Wire VCC to 5V and GND to ground. Place the 10kΩ (R1) and 140kΩ (R2) resistors. (Use a 100kΩ and 40kΩ in series for R2 if 140kΩ is unavailable).
- Connect the Sensor: Plug the bottom plate pigtail into the breadboard GND rail. Plug the top plate pigtail into the THRES/TRIG node. Keep these pigtails as short as physically possible to minimize inductive reactance.
- Verify Output: Connect an oscilloscope or a multimeter with a frequency counter to Pin 3 (OUT). You should read approximately 49.7 kHz. Pressing down on the top plate (compressing the Kapton) should visibly drop the frequency as 'd' decreases.
Failure Modes: What Breaks at the Extremes
When designing physical capacitors, you must account for mechanical and electrical extremes. Here is the failure-mode contrast for this specific topology.
Extreme 1: Dielectric Breakdown (Short Circuit, d = 0)
If the Kapton tape tears or the copper edges fold over and touch, the plates short together. Theoretically, capacitance becomes infinite. In the circuit, the THRES/TRIG node is pulled directly to GND. The TLC555's internal discharge MOSFET (Pin 7) turns on hard, attempting to pull an already-low node to ground. Because R1 (10kΩ) limits the current from VCC to roughly 0.5 mA, the IC will survive, but the output (Pin 3) will lock HIGH or LOW depending on the internal latch state, and oscillation ceases entirely.
Extreme 2: Plate Disconnect (Open Circuit, d = ∞)
If a solder joint breaks or a pigtail pulls out, the physical capacitor is removed from the circuit. The THRES/TRIG node is now floating, relying entirely on the breadboard's stray parasitic capacitance to GND (typically 2 pF to 5 pF). Plugging 3 pF into our timing formula pushes the theoretical frequency to ~1.6 MHz. The TLC555 has a maximum specified frequency of roughly 2 MHz (see the Texas Instruments TLC555 Datasheet for propagation delay limits). At this extreme, internal propagation delays cause the duty cycle to collapse, the waveform becomes erratic, and the output may stall completely due to the comparator's inability to resolve the noise floor.
