A two-source Kirchhoff circuit is not just an academic textbook exercise; it is the fundamental topology behind dual-supply redundancy, battery charging networks, and active load sharing. When you tie two different voltage sources together through a shared load, Kirchhoff's Current Law (KCL) and Kirchhoff's Voltage Law (KVL) dictate exactly how current splits, combines, and occasionally flows backward. Understanding this interaction is critical before you ever wire a backup battery to a primary DC bus.

In this guide, we will design a practical dual-loop resistive network, solve for the exact node voltages and branch currents, and map out the failure modes that occur when components open or short at the extremes.

Topology Definition and Node Mapping

To analyze any multi-loop network, you must first establish a rigid node map and define your loop directions. Our circuit consists of two DC voltage sources feeding a shared central load resistor.

  • Node 1: 12V DC Source (V1) positive terminal.
  • Node 2: 5V DC Source (V2) positive terminal.
  • Node A: The central junction where Branch 1, Branch 2, and the Load meet.
  • Node 0: Common Ground (0V reference).

Branch 1 connects Node 1 to Node A via resistor R1. Branch 2 connects Node 2 to Node A via resistor R2. The load resistor R3 connects Node A to Node 0. This creates two distinct loops: Loop 1 (V1 → R1 → R3 → GND) and Loop 2 (V2 → R2 → R3 → GND).

Bench Tip: Always assume current flows out of the positive terminal of your sources when setting up KVL equations. If the math yields a negative current, it simply means the physical current is flowing in the opposite direction—a common occurrence in multi-source circuits known as back-feeding.

Component Spec Sheet and Design Values

Before solving the equations, we must select real-world components. We are using standard 1% metal film resistors to ensure our calculated node voltages match our multimeter readings on the bench. The following table defines the exact bill of materials for this build.

Designator Component Type Value / Rating Power Dissipation (Calculated) Selected Wattage
V1 DC Bench Supply 12.0V Nominal N/A N/A
V2 DC USB/Bench Supply 5.0V Nominal N/A (Sinking power) N/A
R1 Metal Film Resistor 470Ω, 1% 0.082W 1/2W (0.5W)
R2 Metal Film Resistor 220Ω, 1% 0.007W 1/4W (0.25W)
R3 Metal Film Resistor 1kΩ, 1% 0.039W 1/4W (0.25W)

With these values locked in, we apply Kirchhoff's Circuit Laws to find the voltage at Node A ($V_A$) and the branch currents ($I_1, I_2, I_3$).

Solving the Kirchhoff Equations

Using KCL at Node A, we know the current entering must equal the current leaving: $I_1 + I_2 = I_3$.

Using KVL for Loop 1: $12V - (I_1 imes 470) - (I_3 imes 1000) = 0$
Using KVL for Loop 2: $5V - (I_2 imes 220) - (I_3 imes 1000) = 0$

Substituting $I_3$ with $(I_1 + I_2)$ and solving the simultaneous linear equations yields the following real-world bench values:

  • $I_1$ (Current from 12V source): +12.15 mA
  • $I_2$ (Current from 5V source): -5.86 mA
  • $I_3$ (Current through Load R3): +6.29 mA
  • $V_A$ (Voltage at Node A): 6.29V

The negative value for $I_2$ is the critical insight here. Because $V_A$ (6.29V) is higher than V2 (5.0V), current is actually being forced backward into the 5V source. The 12V supply is doing all the heavy lifting, powering the load and back-feeding the 5V rail.

Behavior Matrix: What Breaks at the Extremes?

A circuit on paper behaves perfectly; a circuit on a breadboard encounters open wires, shorted leads, and failed components. Understanding the failure modes of a Kirchhoff circuit prevents catastrophic damage to your power supplies. The table below details exactly what happens when a single element fails.

Failure Event Effect on Node A Voltage ($V_A$) Effect on Branch 1 (12V) Effect on Branch 2 (5V) Real-World Hazard
R1 Opens Drops to ~4.10V $I_1$ falls to 0 mA $I_2$ becomes positive (+4.1mA) Load loses 12V support; 5V source now powers the entire circuit.
R2 Opens Rises to ~8.14V $I_1$ increases to +8.1mA $I_2$ falls to 0 mA Node A overvoltage. If a 5V microcontroller is tied to Node A, it will be destroyed.
R3 Shorts Drops to 0V $I_1$ spikes to 25.5 mA $I_2$ spikes to 22.7 mA Both supplies dump maximum current into the short. Resistors R1 and R2 must absorb the heat.
V1 Fails (0V) Drops to ~3.48V $I_1$ becomes negative (-7.4mA) $I_2$ increases to +6.9mA The 5V source back-feeds into the dead 12V supply.
Safety Caveat: If V2 is a linear voltage regulator (like an LM7805) rather than a raw battery or bench supply, the -5.86 mA back-feed current will flow into the regulator's output pin. Most linear regulators cannot sink current and will suffer internal junction breakdown or output overvoltage. Always place a reverse-biased Schottky diode (e.g., 1N5819) across the output of linear regulators in multi-source topologies.

Why This Topology Over a Diode-OR'd Supply?

If tying two sources together risks back-feeding, why not just use a Diode-OR configuration (placing a diode in series with each source before they meet at Node A)?

A Diode-OR setup is the industry standard for preventing back-feed. If V1 is 12V and V2 is 5V, the diode on the 5V leg will be reverse-biased, completely isolating V2. However, this introduces two major compromises:

  1. Voltage Drop: Standard silicon diodes drop ~0.7V; Schottky diodes drop ~0.3V. In low-voltage embedded systems (e.g., a 3.3V rail), losing 300mV to a protection diode can push your logic levels out of spec.
  2. No Proportional Sharing: A Diode-OR is a winner-takes-all topology. The higher voltage source supplies 100% of the load until it fails. The lower voltage source sits completely idle, contributing nothing to the system's overall thermal or current capacity.

The direct resistive Kirchhoff topology we analyzed above allows for proportional load sharing based on the source impedances (R1 and R2). While it permits back-feeding, this exact behavior is intentionally utilized in active battery charging circuits and analog current-mirroring networks where the 'back-feed' is actually the desired charge current.

Step-by-Step Breadboard Verification

Do not just trust the math; verify it on the bench. Follow this exact sequence to safely test the circuit and observe KCL in action using a standard digital multimeter (DMM).

Phase 1: Cold Checks (De-energized)

  1. Insert R1 (470Ω), R2 (220Ω), and R3 (1kΩ) into the breadboard, ensuring they share a common ground rail for Node 0.
  2. Set your DMM to continuity/resistance mode.
  3. Measure across R3. You should read exactly 1kΩ (±10Ω). This confirms no accidental short circuits in the breadboard contacts.

Phase 2: Single-Source Baseline

  1. Connect only V1 (12V) to Node 1. Leave Node 2 (V2) completely disconnected.
  2. Set DMM to DC Voltage. Measure Node A relative to Ground. You should read ~8.14V. This is a simple voltage divider between R1 and R3.
  3. Disconnect V1. Connect only V2 (5V) to Node 2.
  4. Measure Node A. You should read ~4.10V. This is the voltage divider between R2 and R3.

Phase 3: Dual-Source and Current Measurement

  1. Connect both V1 (12V) and V2 (5V) simultaneously.
  2. Measure Node A. The voltage will settle at 6.29V. Notice how it sits between the two single-source baselines, pulled higher by the 12V source.
  3. Set your DMM to the mA current range. Break the circuit at Branch 2 (between V2 and R2) and insert the meter in series.
  4. Observe the reading. Your meter will display -5.86 mA (or a positive value if your red probe is facing Node A instead of V2). This physically proves that current is flowing backward into the 5V supply, validating the KCL node equation.

By building and measuring this specific Kirchhoff circuit, you move beyond abstract formulas and develop an intuitive feel for how node voltages shift when multiple sources compete. This foundational understanding is what separates parts-swappers from true circuit designers.