The Direct Answer: What Is a Junction Field Effect Transistor?
A Junction Field Effect Transistor (JFET) is a three-terminal, voltage-controlled semiconductor device where current flows through a physical channel between the Drain and Source terminals, regulated by an electric field generated by the Gate terminal. Unlike Bipolar Junction Transistors (BJTs) which are current-controlled, or enhancement-mode MOSFETs which are normally off, a JFET is a depletion-mode, normally-on device. With zero voltage applied to the Gate, maximum current flows. Applying a reverse-bias voltage to the Gate 'pinches off' the channel, restricting current flow.
Because the Gate forms a reverse-biased PN junction with the channel, the input impedance is exceptionally high (typically >10^9 ohms), drawing virtually zero DC gate current. This makes JFETs the undisputed champions of high-impedance sensor buffering, low-noise audio preamplifiers, and RF front-ends. For a deeper look at the semiconductor physics governing the depletion region, All About Circuits provides an excellent foundational breakdown.
Pinout and Symbol Identification
JFETs come in N-channel and P-channel varieties. The schematic symbol features a vertical line representing the channel, with the Drain at the top and Source at the bottom. The Gate is an arrow pointing into the channel for N-channel (arrow points IN) and outward for P-channel (arrow points OUT).
For the ubiquitous TO-92 through-hole package (like the 2N5457), hold the flat side facing you with the leads pointing down. The standard pinout from left to right is:
- Pin 1: Drain
- Pin 2: Source
- Pin 3: Gate
JFET Operation Regions and Safe Default Part Numbers
To use a JFET effectively, you must bias it into the correct operating region. The behavior of the device changes drastically depending on the Drain-Source voltage (V_DS) and Gate-Source voltage (V_GS).
| Region | Conditions | Typical Voltages / Currents | Practical Application |
|---|---|---|---|
| Cutoff | V_GS < V_GS(off) | V_GS = -3V to -6V (N-ch), I_D ≈ 0A | Solid-state switching (OFF state) |
| Ohmic (Linear) | V_DS < V_GS - V_GS(off) | V_DS < 1V, I_D varies linearly | Voltage-controlled resistors, AGC circuits |
| Saturation (Active) | V_DS > V_GS - V_GS(off) | V_DS = 2V to 15V, I_D is constant | Amplifiers, constant current sources |
| Breakdown | V_DS exceeds BV_DSS | V_DS > 25V (typ), I_D spikes | Destructive failure (Avoid) |
Safe Default Part Numbers for 2026 Builds
While the legendary MPF102 is mostly found in old parts bins or as overpriced counterfeits online, modern production alternatives are readily available and cheap ($0.50 to $1.50 each in low quantities).
- 2N5457 (N-Channel): The ultimate general-purpose audio JFET. V_DS(max) = 25V, I_DSS = 1.0 to 5.0 mA, V_GS(off) = -0.5V to -6.0V. Perfect for guitar pedals and microphone preamps.
- J310 (N-Channel): Designed for VHF/UHF RF applications. V_DS(max) = 25V, I_DSS = 24 to 60 mA. High transconductance makes it ideal for antenna preamplifiers and RF oscillators.
- LSK170 (N-Channel): An ultra-low noise JFET (0.9 nV/√Hz at 1kHz). V_DS(max) = 40V. Expensive ($4-$8 each), but mandatory for high-end studio microphone preamps and precision sensor front-ends.
How to Bias a JFET: A Complete Audio Preamp Circuit
The most common and stable way to bias a JFET for amplification is the Self-Bias Common-Source configuration. Because JFETs have wide manufacturing tolerances in their I_DSS (zero-gate-voltage drain current) and V_GS(off) parameters, fixed-voltage biasing is unreliable. Self-biasing uses a source resistor to automatically stabilize the operating point.
Here is a complete, bench-tested circuit for a high-impedance acoustic guitar or piezo pickup preamplifier using a 2N5457.
Component List and Values
- Q1: 2N5457 N-Channel JFET
- V_DD: 9V to 12V DC regulated supply
- R_D (Drain Resistor): 10 kΩ (Sets drain voltage and gain)
- R_S (Source Resistor): 1 kΩ (Sets the bias current)
- R_G (Gate Resistor): 2.2 MΩ (Provides DC path to ground for gate leakage current, sets input impedance)
- C_IN (Input Coupling): 1 µF film capacitor
- C_OUT (Output Coupling): 10 µF film or low-ESR electrolytic
- C_S (Source Bypass): 47 µF electrolytic (Bypasses R_S for AC signals to maximize voltage gain)
Biasing Math and Operation
The Gate is tied to ground via the 2.2 MΩ resistor (R_G), meaning the DC voltage at the Gate (V_G) is exactly 0V. The Drain current (I_D) flows through the 1 kΩ source resistor (R_S), creating a positive voltage at the Source (V_S). Assuming a typical 2N5457 settles at I_D = 1.5 mA in this circuit:
V_S = I_D × R_S = 1.5mA × 1kΩ = 1.5V
Because V_G = 0V, the Gate-to-Source voltage becomes:
V_GS = V_G - V_S = 0V - 1.5V = -1.5V
This -1.5V reverse-bias automatically pinches the channel just enough to stabilize the current. If the specific JFET tries to draw more current, V_S increases, making V_GS more negative, which pinches the channel further and reduces the current. This negative feedback loop guarantees a stable DC operating point regardless of which specific 2N5457 you pull from the bin. For more advanced biasing topologies, refer to the JFET amplifier guides on Electronics Tutorials.
Failure Modes and Multimeter Testing
JFETs are remarkably rugged regarding thermal runaway (unlike BJTs), but they are highly susceptible to Electrostatic Discharge (ESD) and Gate-Source reverse breakdown. The Gate-Source junction is a standard PN diode; if the reverse voltage exceeds V_GS(off) by a wide margin (typically >25V to 30V), the junction avalanches and shorts out. Once the Gate shorts to the Source, the JFET loses its ability to pinch off the channel and becomes a permanently 'ON' resistor.
How to Test a JFET with a Digital Multimeter
You can verify the health of an N-channel JFET using the Diode Test mode on a standard DMM. Remove the JFET from the circuit before testing to avoid parallel resistance paths.
- Identify Pins: Confirm Drain, Source, and Gate using the datasheet.
- Test Gate-Source Junction (Forward): Place the Red (positive) probe on the Gate and the Black (negative) probe on the Source. A healthy N-channel JFET will read between 0.500V and 0.750V.
- Test Gate-Source Junction (Reverse): Swap probes (Black on Gate, Red on Source). The meter must read OL (Over Limit). If it reads a low voltage or 0.000, the Gate is shorted; discard the part.
- Test Gate-Drain Junction: Repeat steps 2 and 3 between Gate and Drain. You should get the exact same diode-drop and OL readings.
- Test Drain-Source Channel: Set the meter to Resistance (Ω) mode. Place probes across Drain and Source (polarity doesn't matter for this step). You should read a resistance typically between 100 Ω and 1,000 Ω (this is the R_DS(on) of the unpinched channel). If it reads OL, the internal channel is blown open.
Frequently Asked Questions About JFETs
What is the difference between a JFET and a MOSFET?
The fundamental difference lies in the Gate structure. A JFET uses a physical PN junction to create the depletion region that controls the channel, meaning the Gate is a diode. A MOSFET (Metal-Oxide-Semiconductor FET) uses a layer of silicon dioxide insulation between the Gate and the channel. Consequently, a MOSFET has practically infinite DC input impedance and draws zero gate leakage current, while a JFET has a very high (but finite) impedance and a tiny reverse-leakage current. Furthermore, JFETs are exclusively depletion-mode (normally ON), whereas MOSFETs are available in both enhancement-mode (normally OFF) and depletion-mode.
Why do JFETs have such high input impedance?
The input impedance is high because the Gate-Channel junction is operated in reverse-bias. In a reverse-biased PN junction, the depletion region widens, preventing majority carriers from crossing the junction. The only current that flows is the minor reverse-leakage current, which is typically in the picoampere (pA) range. Since Impedance (Z) = Voltage / Current, dividing a voltage by a picoamp-level current yields an input impedance in the hundreds of megohms to gigohms range.
Can I use an N-channel JFET as a direct replacement for an NPN BJT?
No, they are not drop-in replacements. An NPN BJT is a current-controlled device that requires base current to turn on, and it is normally OFF. An N-channel JFET is a voltage-controlled device that requires a negative gate voltage to turn off, and it is normally ON. If you replace an NPN BJT with a JFET in a standard switching circuit, the JFET will remain permanently turned on (conducting Drain to Source) because the Gate is not receiving the negative reverse-bias voltage required to pinch off the channel. You must redesign the biasing network entirely to swap the two.
Are JFETs still used in modern 2026 circuit designs?
Absolutely. While CMOS and BiCMOS processes dominate digital and mixed-signal ICs, discrete JFETs remain irreplaceable in specific analog niches. In 2026, they are still the standard for ultra-low-noise audio preamplifiers (like those found in Neumann and Schoeps microphones), high-impedance piezo sensor buffers, and specialized RF front-ends where the 1/f (flicker) noise of MOSFETs is unacceptable. Furthermore, JFETs are heavily used as analog switches and multiplexers in precision data acquisition systems because they lack the gate-charge injection artifacts that plague MOSFET switches.






