At the workbench, boolean algebra and truth tables are not just abstract math—they are the physical blueprints for how voltage moves through silicon. Boolean algebra provides the mathematical rules (AND, OR, NOT) to simplify logic circuits, while a truth table maps every possible combination of physical input pins to a definitive output state (High or Low). If you are designing a custom control board, debugging a stuck relay, or interfacing a 5V microcontroller with a 12V system, you need to know exactly which IC package executes which boolean expression, and how fast it does it.
This reference guide bridges the gap between textbook theory and physical hardware. Below, you will find the master lookup table for standard combinatorial logic gates, complete with physical IC part numbers, propagation delays, and the industry standards that govern their symbols.
The Master Logic Gate Reference Table
How to read this table: This chart maps the theoretical boolean expression to physical, off-the-shelf DIP/SOIC integrated circuits. The Symbol Standard column references the dual-standard recognized globally: ANSI/IEEE Std 91-1984 (the traditional military/aerospace rectangular shapes) and IEC 60617-12 (the European standard). The Typ. $t_{pd}$ column lists the typical propagation delay at a 5V supply with a 50 pF capacitive load. Use the 74HC column for modern 5V/3.3V digital designs, and the 4000 series column for legacy or high-voltage (up to 15V) applications.
| Gate Type | Boolean Expression | Symbol Std. | 74HC Series IC (Quad) | CD4000 Series IC | Typ. $t_{pd}$ (5V) |
|---|---|---|---|---|---|
| AND | $Y = A \cdot B$ | IEEE 91 / IEC 60617 | 74HC08 | 4081 | 14 ns |
| OR | $Y = A + B$ | IEEE 91 / IEC 60617 | 74HC32 | 4071 | 14 ns |
| NAND | $Y = \overline{A \cdot B}$ | IEEE 91 / IEC 60617 | 74HC00 | 4011 | 12 ns |
| NOR | $Y = \overline{A + B}$ | IEEE 91 / IEC 60617 | 74HC02 | 4001 | 14 ns |
| XOR | $Y = A \oplus B$ | IEEE 91 / IEC 60617 | 74HC86 | 4070 | 16 ns |
| XNOR | $Y = \overline{A \oplus B}$ | IEEE 91 / IEC 60617 | 74HC266 | 4077 | 18 ns |
- NAND (74HC00 / 4011): The universal gate. You can build any other boolean function using only NAND gates. It is the most common chip in a well-stocked bench kit.
- XOR (74HC86 / 4070): Essential for binary adders and parity generators. Note that XNOR (74HC266) often features open-drain outputs in specific sub-families (like 74HC136), requiring a pull-up resistor.
Which Column Applies: Voltage Thresholds and Logic Families
When deciding between the 74HC and CD4000 columns for your installation, the deciding factor is your system's voltage rail and the required logic thresholds. A truth table tells you that an input of '1' yields an output of '1', but it does not tell you what physical voltage constitutes a '1'.
For the 74HC family (High-speed CMOS), the supply voltage ($V_{CC}$) range is strictly 2.0V to 6.0V. At a nominal 5.0V supply, the guaranteed input high voltage ($V_{IH}$) is 3.5V, and the maximum input low voltage ($V_{IL}$) is 1.5V. If you feed a 74HC08 AND gate a 2.5V signal from an older microcontroller, it sits in the undefined transition region and may oscillate.
For the CD4000 series, the $V_{CC}$ range is much wider: 3.0V to 15.0V. The logic thresholds scale proportionally with the supply rail (typically $0.7 \times V_{CC}$ for a High, and $0.3 \times V_{CC}$ for a Low). If you are building a circuit that interfaces directly with a 12V lead-acid battery monitoring system, the CD4000 column applies to your design. However, be aware that CD4000 propagation delays are significantly longer—often 60 ns to 120 ns at 5V—making them unsuitable for high-speed data buses.
For a deeper dive into voltage translation between these families, Texas Instruments' "Designing with Logic" application note (SDYA009C) remains the definitive bench reference for mixing TTL and CMOS voltage thresholds.
How Loading and Fan-Out Derate Base Truth Table Values
In wire sizing, temperature and conduit fill derate your base ampacity. In digital logic, capacitive loading and fan-out derate your base propagation delay ($t_{pd}$) and noise margins. The truth table assumes an ideal, instantaneous state change. In physical reality, every logic gate input acts as a small capacitor.
A standard 74HC series input has a capacitance of roughly 3.5 pF. If you take the output of a single 74HC00 NAND gate and wire it to the inputs of eight other gates (a fan-out of 8), you are adding $8 \times 3.5 \text{ pF} = 28 \text{ pF}$ of capacitive load to the driver's output transistor.
The derating formula for propagation delay is:
$t_{pd(actual)} = t_{pd(base)} + (C_{load} \times \text{Delay Factor})$
For a 74HC gate at 5V, the delay factor is approximately 0.5 ns per pF of added load. Therefore, driving 28 pF of extra capacitance adds 14 ns of delay to the base 12 ns listed in the table. Your actual switching time is now 26 ns. If you are designing a clocked circuit running at 20 MHz (50 ns period), this derating eats up more than half your timing budget, potentially causing setup-time violations in downstream flip-flops. Always calculate the physical fan-out; never assume the truth table's instantaneous transition holds true under heavy capacitive loading.
What the Truth Table Cannot Tell You: Edge Cases and Failures
Boolean algebra assumes binary perfection: a pin is either a 0 or a 1. The physical silicon disagrees. Here is what the reference table leaves out, which you must account for on the bench:
- Floating Inputs and Shoot-Through Current: A truth table has no row for an "unconnected" input. If you leave a CMOS input pin floating, it will pick up ambient electromagnetic noise and drift into the linear region (between $V_{IL}$ and $V_{IH}$). In this state, both the PMOS and NMOS transistors inside the gate turn on simultaneously, creating a direct short from $V_{CC}$ to GND. This "shoot-through" current will cause the IC to overheat and fail. Rule: Every unused CMOS input must be tied to VCC or GND via a 10k$\Omega$ resistor.
- Simultaneous Switching Noise (SSN): If you use a 74HC32 (Quad OR) and all four outputs switch from High to Low at the exact same nanosecond, the sudden rush of current through the ground pin's parasitic inductance causes the local ground reference to spike upward (ground bounce). This can falsely trigger other gates sharing the same ground return. The fix is proper decoupling: place a 100 nF ceramic capacitor directly across the $V_{CC}$ and GND pins of every single logic IC, as close to the package body as physically possible.
- Metastability in Sequential Logic: While this chart covers combinatorial gates, remember that when boolean outputs feed into latches or flip-flops, violating the setup or hold time windows will result in a metastable state—a physical voltage hovering between 0 and 1 that the truth table cannot predict.
For comprehensive theory and physical layer explanations of these edge cases, the All About Circuits Digital Textbook provides excellent oscilloscope captures showing exactly what ground bounce and floating inputs look like in real time. Boolean algebra gives you the logic; understanding the silicon gives you a working circuit.
