A discrete NMOS NAND gate circuit diagram uses N-channel MOSFETs in series to pull the output node low only when both inputs are high. Unlike standard 74HC logic ICs that hide the internal transistor physics inside a black plastic package, building this gate discretely exposes the raw mechanics of digital logic. For this design, we are using two 2N7000 N-channel MOSFETs, a 10kΩ pull-up resistor, and two 10kΩ gate pull-down resistors. This configuration operates reliably from 3.3V to 5V DC, making it ideal for interfacing between microcontrollers and higher-voltage relays or indicator circuits.
Topology Description & Node Labels
To understand the fundamentals of digital logic gates, we must map the physical components to logical nodes. The NMOS NAND topology relies on a passive pull-up network and an active pull-down network.
- Node VDD: The positive supply rail (typically +5V DC).
- Node GND: The 0V reference ground.
- Node A & Node B: The logic inputs. Driven by microcontroller GPIOs or tactile switches.
- Node Y: The logic output. This is the junction between the pull-up resistor and the drain of the first MOSFET.
R1 (Pull-up): 10kΩ resistor connected from VDD to Node Y. This weakly pulls Y HIGH when the MOSFETs are off.
Q1 & Q2 (Switches): 2N7000 MOSFETs wired in series. Q1 Drain connects to Node Y; Q1 Source connects to Q2 Drain; Q2 Source connects to GND.
R2 & R3 (Gate Pull-downs): 10kΩ resistors from Gate to GND on both Q1 and Q2. These prevent floating gates from accumulating static charge and accidentally turning the transistors on.
Why NMOS Over RTL or Standard ICs?
You might wonder why we use this specific NMOS topology rather than Resistor-Transistor Logic (RTL) using BJTs, or just buying a $0.20 74HC00 IC. RTL suffers from continuous base current draw and slower switching speeds due to minority carrier storage time. Standard CMOS ICs are excellent for production, but they are optimized for silicon area, not educational transparency or high-voltage tolerance. A discrete 2N7000 NMOS gate offers near-zero static gate current (high input impedance) and can tolerate drain voltages up to 60V, allowing Node Y to switch a 12V relay coil directly if you adjust the pull-up resistor to VDD=12V—something a standard 5V TI logic IC would instantly destroy.
Behavior Matrix & Extreme Failure Modes
The core logic function is a NAND operation: the output is LOW only if both A and B are HIGH. Below is the behavioral matrix detailing the internal state of the circuit.
| Input A | Input B | Q1 State | Q2 State | Node Y Voltage | Logic Output |
|---|---|---|---|---|---|
| LOW (0V) | LOW (0V) | OFF | OFF | ~4.9V | HIGH (1) |
| HIGH (5V) | LOW (0V) | ON | OFF | ~4.9V | HIGH (1) |
| LOW (0V) | HIGH (5V) | OFF | ON | ~4.9V | HIGH (1) |
| HIGH (5V) | HIGH (5V) | ON | ON | ~0.15V | LOW (0) |
What Changes When One Element Changes?
Circuit behavior is highly dependent on component tolerances and failure states. Here is how the circuit reacts when specific elements drift or fail:
| Element Altered | Change Type | Impact on Circuit Behavior |
|---|---|---|
| R1 (Pull-up) | Increases to 100kΩ | Rise time of Node Y slows significantly; output becomes highly susceptible to EMI noise and parasitic capacitance. |
| R1 (Pull-up) | Decreases to 1kΩ | Faster rise times, but static current draw when output is LOW jumps from 0.5mA to 5mA, wasting power and heating Q1/Q2. |
| R2/R3 (Pull-downs) | Removed (Open) | Gates float. Ambient electromagnetic fields can induce enough voltage to partially turn on Q1/Q2, causing unpredictable output oscillation. |
| Q1 (MOSFET) | Drain-Source Short | Circuit degrades into a simple inverter controlled solely by Input B. Node Y goes LOW whenever B is HIGH, regardless of A. |
If a stray solder bridge or jumper wire shorts VDD directly to Node Y, the pull-up resistor is bypassed. Node Y will be permanently stuck HIGH. Worse, if both inputs are subsequently driven HIGH, Q1 and Q2 will create a dead short from the 5V rail directly to GND. With no current-limiting resistor in the drain path, the 2N7000s will attempt to pull amps of current, rapidly exceeding their 200mA continuous drain rating and causing the silicon die to overheat and fail catastrophically.
Step-by-Step Breadboard Verification
Translating a gate circuit diagram from paper to a physical breadboard requires strict attention to the 2N7000 pinout. When holding the transistor with the flat face toward you and the pins pointing down, the pins from left to right are: Gate (1), Source (2), Drain (3).
- Establish Power Rails: Connect your bench power supply to the breadboard rails. Set it to 5.0V. Place a 100nF ceramic decoupling capacitor across the VDD and GND rails near the center of the board to suppress high-frequency ringing caused by long jumper wires.
- Place the Switches: Insert Q1 and Q2 into the breadboard, ensuring they straddle the center gap. Wire Q1 Source (pin 2) directly to Q2 Drain (pin 3) using a short jumper. Wire Q2 Source (pin 2) to the GND rail.
- Wire the Pull-Up: Insert the 10kΩ R1 resistor. Connect one leg to the VDD rail and the other leg to Q1 Drain (pin 3). This junction is your Node Y.
- Install Gate Pull-Downs: Insert R2 and R3 (10kΩ each). Connect one leg of R2 to Q1 Gate (pin 1) and the other to GND. Repeat for R3 on Q2 Gate (pin 1).
- Pre-Flight Multimeter Check: Before applying logic signals, set your DMM to continuity mode. Verify there is no short between VDD and GND. Verify the resistance between Node Y and GND reads roughly 10kΩ (the pull-up resistor value, since the MOSFETs are off).
- Apply Logic and Measure: Use jumper wires to connect Input A and Input B to either VDD (HIGH) or GND (LOW). Connect your DMM positive probe to Node Y. Cycle through the four states in the behavior matrix. You should read ~4.9V for the first three states, and drop to ~0.15V when both A and B are connected to VDD.
Frequently Asked Questions
How do I read a standard CMOS gate circuit diagram vs this discrete NMOS version?
A standard CMOS (Complementary MOS) gate circuit diagram replaces the passive 10kΩ pull-up resistor with a network of P-channel MOSFETs. In a CMOS NAND gate, the PMOS transistors are wired in parallel between VDD and Node Y. When either input goes LOW, the corresponding PMOS turns ON, actively driving the output HIGH with low impedance. The discrete NMOS version we built uses a resistor for the pull-up, which is cheaper and simpler to breadboard, but results in an asymmetrical drive strength: it can sink current (pull LOW) much faster and stronger than it can source current (pull HIGH through the 10kΩ resistor).
Why is my discrete gate circuit diagram outputting a weak HIGH signal?
If your Node Y reads 4.9V on a multimeter but fails to light an LED or trigger the next logic stage, you are experiencing a high-impedance output limitation. The 10kΩ pull-up resistor limits the maximum source current to roughly 0.5mA (5V / 10,000Ω). A standard red LED requires 10mA to 20mA to illuminate brightly. If you connect an LED directly from Node Y to GND, the voltage at Node Y will collapse to the LED's forward voltage (~2V), which is below the logic HIGH threshold for most 5V systems. To fix this, either buffer the output with a dedicated MOSFET driver, or lower the pull-up resistor to 470Ω (warning: this increases static power dissipation when the output is LOW to ~10mA).
Can I cascade this NMOS gate circuit diagram to build an AND gate?
Yes. An AND gate is simply a NAND gate followed by an inverter (NOT gate). To build the inverter discretely on the same breadboard, you need one additional 2N7000 (Q3), one 10kΩ pull-up resistor (R4), and one 10kΩ gate pull-down (R5). Connect Node Y from your NAND gate to the Gate of Q3. Wire R4 from VDD to Q3 Drain (this new junction is your final AND output). Wire Q3 Source to GND, and R5 from Q3 Gate to GND. When Node Y is HIGH, Q3 turns ON and pulls the final output LOW. When Node Y is LOW, Q3 turns OFF and R4 pulls the final output HIGH, completing the AND logic function.
