DC bus capacitor sizing is the process of selecting a capacitor bank that limits DC link voltage ripple to acceptable bounds while surviving the RMS ripple current heating without exceeding its thermal limits. When interviewers ask about this, they aren't just testing your ability to memorize a formula; they are filtering for engineers who understand the physical realities of power conversion.
In a real circuit, the DC bus capacitor changes the stability of the entire power stage. It dictates the physical volume of the inverter, sets the cooling requirements, and prevents undervoltage lockouts in your gate drivers during high-transient load steps. If you undersize it, your DC link voltage sags, causing erratic PWM behavior and potential shoot-through faults in your IGBTs or MOSFETs.
What people commonly confuse it with is the difference between peak-to-peak voltage ripple ($\Delta V$) and RMS ripple current ($I_{rms}$). Junior engineers will calculate the capacitance required to hold the voltage steady and stop there. Senior engineers know that the RMS ripple current physically destroys the capacitor via internal $I^2R$ heating in the Equivalent Series Resistance (ESR), which is usually the actual limiting factor in high-power designs.
The Core Concept: What the Interviewer is Actually Asking
Think of the DC bus capacitor as a local water tower for a city grid: it doesn't generate the water (power), but it absorbs the sudden pressure drops when a million toilets flush at once (switching transients). In a 3-phase inverter, the DC link sees high-frequency switching ripple (from the PWM carrier frequency, often 10kHz-20kHz) and low-frequency ripple (at twice the fundamental output frequency, e.g., 120Hz for a 60Hz motor).
The Worked Numeric Example: Sizing for a 5kW Inverter
Let's walk through the exact math you should write on the whiteboard. Assume you are designing a 5kW, 3-phase motor drive with a 400V DC bus, targeting a maximum voltage ripple of 2.5% (10V peak-to-peak), driving a 60Hz motor.
Step 1: Calculate Required Capacitance
First, find the average DC current: $I_{dc} = P / V_{dc} = 5000W / 400V = 12.5A$.
The worst-case low-frequency ripple occurs at twice the fundamental frequency ($2 \times 60Hz = 120Hz$). Using the standard approximation for 3-phase inverters:
$C = \frac{I_{dc}}{2 \pi \cdot f_{ripple} \cdot \Delta V}$
$C = \frac{12.5}{2 \pi \cdot 120 \cdot 10} = \frac{12.5}{7539} \approx 1658 \mu F$
You would select a standard value, such as two 1000\mu F capacitors in parallel (yielding 2000\mu F).
Step 2: Calculate RMS Ripple Current and Thermal Limits
Here is where the real engineering happens. For a 3-phase inverter using Space Vector PWM (SVPWM), the worst-case RMS ripple current in the DC bus capacitor is approximately $0.65 \times I_{peak}$. Assuming a peak phase current of 20A, the capacitor bank must handle:
$I_{cap(rms)} \approx 0.65 \times 20A = 13A$
If your chosen 1000\mu F capacitor has a rated ripple current of 4A at 105°C, two in parallel only give you 8A. You will overheat and vent the capacitors. You must either parallel four capacitors (4 x 4A = 16A > 13A) or select a larger physical can size with a higher ripple rating. Furthermore, you must calculate the internal power dissipation:
$P_{loss} = I_{rms}^2 \times ESR_{total}$
If the ESR of one cap is 80m\Omega, four in parallel yields 20m\Ω. $P_{loss} = 13^2 \times 0.020 = 3.38W$. You then check the manufacturer's thermal resistance ($R_{th}$) curve to ensure this 3.38W dissipation doesn't push the internal hotspot temperature past the 105°C maximum limit.
Where You Meet This in Practice
You will encounter DC bus capacitor sizing in almost every power electronics application, but the implementation varies wildly based on the environment:
- Industrial VFDs (Variable Frequency Drives): Typically use large banks of snap-in or screw-terminal aluminum electrolytic capacitors. The primary failure mode here is electrolyte boil-off due to high ambient temperatures in control panels, leading to ESR drift and eventual cascading MOSFET failures.
- EV Traction Inverters: Modern 800V EV architectures (like those in Porsche or Hyundai platforms) have almost entirely abandoned electrolytics in the DC link. They use metallized polypropylene (MKP) film capacitors because they must survive severe vibration, thermal cycling from -40°C to +125°C, and require a 15-year operational lifespan without capacitance degradation.
- Solar String Inverters: Often use a hybrid approach. Film capacitors handle the high-frequency switching ripple close to the power modules, while a smaller bank of electrolytics handles the low-frequency 120Hz bulk energy buffering from the grid tie.
Decision Path: Selecting the Right Capacitor Technology
When the interviewer asks, 'Which capacitor technology would you choose and why?', use this decision matrix to justify your pick.
| Criteria | Aluminum Electrolytic (Snap-in) | Metallized Polypropylene (MKP Film) | Multilayer Ceramic (MLCC) |
|---|---|---|---|
| Energy Density ($\mu F / cm^3$) | Very High (Best for bulk storage) | Moderate (Requires more PCB/Busbar space) | Low (Only for HF decoupling) |
| RMS Ripple Capability | Moderate (Limited by ESR heating) | Very High (Extremely low ESR) | High (But limited by physical size/cost) |
| Operating Temp Limit | 85°C to 105°C (Typical) | 105°C to 125°C (Automotive grade) | 125°C to 150°C (X8R/X9E dielectrics) |
| Lifespan / Reliability | 2,000 - 10,000 hours (Wears out) | >100,000 hours (Self-healing, no wear-out) | >100,000 hours (Risk of mechanical cracking) |
| Cost per $\mu F$ | Lowest | 3x to 5x higher | 10x to 50x higher |
The Default Recommendation
Do not end your interview answer with 'it depends on the application.' Give a concrete default based on modern industry trends.
If designing a cost-constrained, stationary 5kW industrial VFD: The default pick is the Cornell Dubilier 381LX series snap-in aluminum electrolytic (e.g., 381LX102M450A). It offers the lowest BOM cost and high energy density, and the 3-year warranty profile of industrial equipment aligns with the 5,000-hour lifespan of the caps at rated temperature.
If designing a 400V/800V EV traction inverter or high-reliability solar inverter: The default pick is the TDK B32778G series (ModCap or boxed MKP film). The self-healing dielectric, ability to handle massive RMS ripple currents without active liquid cooling, and 15-year lifespan justify the higher upfront cost and larger physical footprint.
Rapid-Fire FAQ: Other Common Interview Traps
Q: Why do interviewers ask about the Miller Plateau when discussing MOSFET switching?
Answer: The Miller plateau is the flat region on the $V_{gs}$ (gate-to-source voltage) vs. gate charge graph where the gate driver current is entirely consumed charging the gate-to-drain capacitance ($C_{gd}$) as the drain voltage swings. It matters because the duration of the Miller plateau dictates your switching losses ($E_{on}$ and $E_{off}$). If you don't size your gate resistor to source enough peak current to cross the plateau quickly, your MOSFET will spend too much time in the linear region and overheat.
Q: How does skin effect change your DC busbar sizing at high switching frequencies?
Answer: At DC, current flows through the entire cross-section of a copper busbar. But at a 20kHz PWM switching frequency (and its harmonics), the skin depth in copper shrinks to roughly 0.46mm at 20kHz and 0.21mm at 100kHz. If you use a solid 10mm thick copper bar, the center 8mm is carrying almost zero high-frequency current, effectively increasing your AC resistance and causing localized heating. The fix is to use multiple stacked copper strips or Litz-wire bus structures to maximize surface area.
Q: What is the difference between dV/dt rating and surge voltage rating in film capacitors?
Answer: Surge voltage ($V_s$) is the maximum absolute peak voltage the dielectric can withstand without puncturing (usually 1.1 to 1.25 times $V_{rated}$). The $dV/dt$ rating (V/$\mu s$) is the maximum rate of voltage change the internal metallization and spray contacts can handle before the localized current density vaporizes the metal layer, causing an open circuit. In high-speed SiC (Silicon Carbide) inverter circuits, the massive $dV/dt$ (often >50 V/ns) will destroy a capacitor long before the peak surge voltage is reached.
For further reading on component derating and thermal modeling, refer to the application guides provided by Cornell Dubilier and the TDK Film Capacitor technical documentation. Mastering these calculations transitions you from a textbook graduate to a practicing power electronics engineer.
