Designing a Half Adder and Full Adder Circuit Diagram with 74HC Logic

A half adder is a combinational logic circuit that adds two single binary digits (A and B), producing a Sum (Σ) and a Carry (Cout). A full adder expands this by adding a third Carry-in (Cin) input, allowing multiple adders to be cascaded for multi-bit arithmetic. While you can simulate these in software, building a physical half adder and full adder circuit diagram on a breadboard using discrete 74HC-series logic gates reveals the physical realities of propagation delay, floating inputs, and current limiting that simulators hide.

This guide walks through the physical design, node topology, and failure modes of building these adders using Texas Instruments SN74HC CMOS logic ICs operating at 5V.

Logic Topology, Node Mapping, and Timing Specs

To build a full adder from discrete gates, we use the XOR-based topology rather than a raw Sum-of-Products (SOP) Boolean expansion. The circuit requires two XOR gates, two AND gates, and one OR gate. We map these to three specific 14-pin DIP ICs: the SN74HC86N (Quad XOR), SN74HC08N (Quad AND), and SN74HC32N (Quad OR).

Before wiring, we must define the internal nodes. Let A and B be the primary inputs, and Cin be the carry input. The internal nodes are:

• N1: Output of the first XOR gate (A ⊕ B)
• N2: Output of the first AND gate (A · B)
• N3: Output of the second XOR gate (N1 ⊕ Cin), which becomes the final Sum (Σ)
• N4: Output of the second AND gate (N1 · Cin)
• Cout: Output of the OR gate (N2 + N4), the final Carry-out

Below is the data-dense specification and truth table mapping the logical states to the physical IC pins and expected timing.

Input A (Pin)	Input B (Pin)	Cin (Pin)	Sum Σ (Pin)	Cout (Pin)	Gate Depth	Max Prop Delay (74HC @ 5V)
0 (86:1,2)	0 (86:1,2)	0 (86:4,5)	0 (86:6)	0 (32:3)	2 levels	~18 ns (XOR) + 14 ns (OR)
1 (86:1,2)	0 (86:1,2)	0 (86:4,5)	1 (86:6)	0 (32:3)	2 levels	~18 ns (XOR) + 14 ns (OR)
1 (86:1,2)	1 (86:1,2)	0 (86:4,5)	0 (86:6)	1 (32:3)	2 levels	~14 ns (AND) + 14 ns (OR)
1 (86:1,2)	1 (86:1,2)	1 (86:4,5)	1 (86:6)	1 (32:3)	3 levels	18ns + 14ns + 14ns = 46 ns

Note: Pin numbers in parentheses refer to the specific gate inputs/outputs on the 14-pin DIP package. For example, '86:1,2' means pins 1 and 2 of the SN74HC86 IC. Full pinouts are available in the TI SN74HC86 datasheet.

Why the XOR Topology Beats Sum-of-Products

When studying Boolean algebra, you might derive the full adder Sum equation as a canonical Sum-of-Products (SOP): Σ = A'B'Cin + A'BCin' + AB'Cin' + ABCin. Implementing this directly with discrete AND/OR/NOT gates requires four 3-input AND gates, one 4-input OR gate, and three NOT gates. In the 74HC series, this would require at least four separate ICs just for the Sum bit, plus additional ICs for the Carry bit.

The XOR-based topology (Σ = (A ⊕ B) ⊕ Cin) is vastly superior for physical breadboarding for three reasons:

1. Reduced IC Count: The entire full adder fits into just three ICs (one 86, one 08, one 32), leaving unused gates for future expansion or a half-adder demo on the same board.
2. Lower Propagation Delay: The SOP implementation pushes signals through three or four logic levels (NOT -> AND -> OR). The XOR topology resolves the Sum bit in just two logic levels (XOR -> XOR), cutting the worst-case propagation delay nearly in half.
3. Modularity: The first XOR gate (A ⊕ B) and the first AND gate (A · B) perfectly isolate the half adder circuit. You can tap N1 and N2 to demonstrate half-adder functionality without rewiring the board.

Breadboard Design Walkthrough and Component Values

Building digital logic on a solderless breadboard requires strict attention to power integrity and input biasing. Unlike older 74LS (TTL) logic, which internally pulled floating inputs high (albeit noisily), 74HC (CMOS) logic features ultra-high impedance inputs. A floating CMOS input will pick up ambient RF noise, causing the gate to oscillate rapidly between high and low. This oscillation draws massive current and can overheat the IC.

Here are the exact component values required for a stable build:

For a deeper theoretical breakdown of how these gates cascade into ripple-carry adders, Electronics Tutorials provides an excellent mathematical foundation for the carry propagation.

Failure Modes: What Breaks at the Extremes?

When troubleshooting a breadboarded adder, you will inevitably encounter faults. Understanding how the circuit behaves when an element fails is critical for diagnosing issues with a multimeter. Below is the behavior matrix for common physical faults.

Fault Condition	Physical Cause on Breadboard	Circuit Behavior & Symptoms	Resulting Output State
Floating Input (Open)	Missing 10kΩ pull-down resistor on a DIP switch.	CMOS gate oscillates at MHz frequencies. IC becomes hot to the touch. Power supply current spikes from ~2mA to >30mA.	Erratic, random Sum/Cout toggling; LED flickers dimly.
Output Short to GND	LED wired backward or jumper wire bridges output pin to ground rail.	Internal PMOS transistor in the totem-pole output stage attempts to source infinite current. Exceeds 25mA limit.	Output forced LOW. IC may permanently burn out (magic smoke).
Output Short to VCC	Jumper wire bridges output pin to 5V rail.	Internal NMOS transistor attempts to sink infinite current when output goes LOW.	Output forced HIGH. IC overheats and fails.
Un-decoupled Power	Missing 100nF capacitor across IC pins 7 and 14.	Switching transients cause localized VCC sag. Adjacent gates see voltage dips below Vih threshold.	Glitches on Sum/Cout when multiple inputs switch simultaneously.

If your 74HC86 chip is physically warm to the touch, immediately disconnect power. You almost certainly have a floating input or a shorted output trace. For more on digital logic fault isolation, refer to the Wikipedia entry on Adder Electronics which covers structural testing methodologies.

Step-by-Step Verification and Testing

Do not wire the entire full adder and hope it works. Build and verify in stages using a digital multimeter (DMM) set to DC Voltage mode. A logic HIGH should read > 2.0V (typically 4.8V), and a logic LOW should read < 0.8V (typically 0.1V).

1. Stage 1: Power and Decoupling. Wire the 5V and GND rails. Seat all three ICs. Install the 100nF decoupling capacitors directly across the VCC and GND pins of each chip. Power on and verify 5.0V at pin 14 of every IC.
2. Stage 2: The Half Adder Core. Wire inputs A and B (with 10kΩ pull-downs) to the first XOR gate (pins 1, 2) and first AND gate (pins 1, 2 on the 08 chip). Connect LEDs with 330Ω resistors to the XOR output (N1) and AND output (N2).
   Test: Toggle A and B. N1 should be HIGH only when A≠B. N2 should be HIGH only when A=1 and B=1.
3. Stage 3: The Sum Bit. Wire N1 and Cin to the second XOR gate. Connect an LED to the output (N3 / Sum).
   Test: Hold A=1, B=0. Toggle Cin. The Sum LED should toggle exactly with Cin.
4. Stage 4: The Carry-Out Bit. Wire N2 and the output of the second AND gate (N4) into the OR gate (pins 1, 2 on the 32 chip). Connect an LED to the OR output (Cout).
   Test: Set A=1, B=1, Cin=0. Cout should be HIGH. Set A=1, B=0, Cin=1. Cout should be HIGH.
5. Stage 5: Full Cascade Test. Cycle through all 8 binary combinations (000 to 111) using your DIP switches. Verify the outputs match the truth table provided in the first section. If an output fails, use your DMM to probe the internal nodes (N1, N2, N4) to isolate exactly which gate is dropping the signal.

By strictly adhering to CMOS biasing rules and verifying node-by-node, you transform a theoretical half adder and full adder circuit diagram into a robust, physical computing block capable of driving further arithmetic logic units.