A boolean algebra table is the foundational lookup reference for digital circuit design, mapping binary inputs to deterministic logic outputs. Whether you are designing a simple combinational logic circuit on a breadboard or writing hardware description language (HDL) for an FPGA, the abstract mathematics of George Boole must eventually translate into physical voltage states. This reference provides the complete 2-input logic gate truth table, core algebraic identities, and the practical engineering constraints that dictate how these tables behave in real-world silicon.
How to Read the Boolean Algebra Table (Columns & Logic Families)
Before wiring a single 74-series IC, you must understand how to read the table's columns and determine which column applies to your specific installation. A standard truth table lists inputs (A, B) and outputs (Y) as abstract 1s and 0s. However, in physical hardware, a '1' or '0' is entirely dependent on your logic family's voltage thresholds.
If you are using 5V CMOS (e.g., 74HC series), a logic '1' requires $>3.5V$ and a '0' is $<1.5V$. If you are using 5V TTL (e.g., 74LS series), a logic '1' is $>2.0V$ and a '0' is $<0.8V$. Applying a 2.5V signal to a 74HC08 AND gate will result in an undefined state, completely invalidating the boolean algebra table's predicted output. Always check the datasheet's $V_{IH}$ (Input High Voltage) and $V_{IL}$ (Input Low Voltage) columns to map the abstract table to your physical installation.
The rows represent the discrete input permutations. For $n$ inputs, there are $2^n$ rows. A 2-input gate has 4 rows; a 3-input gate has 8 rows. The final column (Y) represents the steady-state DC output after all internal propagation delays have settled.
The Master Boolean Algebra and Truth Table
The following table combines the fundamental 2-input logic gate truth tables with their corresponding boolean algebraic identities. The logic symbols and definitions conform to the ANSI/IEEE Std 91-1984 standard for graphic symbols for logic functions.
Quick-Jump Bookmarks: AND | OR | NAND | NOR | XOR | XNOR
| Logic Gate | Boolean Expression | Input A | Input B | Output Y | Core Identity / Law |
|---|---|---|---|---|---|
| AND | $Y = A \cdot B$ | 0 / 0 / 1 / 1 | 0 / 1 / 0 / 1 | 0 / 0 / 0 / 1 | Intersection / Commutative ($AB = BA$) |
| OR | $Y = A + B$ | 0 / 0 / 1 / 1 | 0 / 1 / 0 / 1 | 0 / 1 / 1 / 1 | Union / Distributive ($A(B+C) = AB+AC$) |
| NAND | $Y = \overline{A \cdot B}$ | 0 / 0 / 1 / 1 | 0 / 1 / 0 / 1 | 1 / 1 / 1 / 0 | De Morgan's: $\overline{AB} = \overline{A} + \overline{B}$ |
| NOR | $Y = \overline{A + B}$ | 0 / 0 / 1 / 1 | 0 / 1 / 0 / 1 | 1 / 0 / 0 / 0 | De Morgan's: $\overline{A+B} = \overline{A} \cdot \overline{B}$ |
| XOR | $Y = A \oplus B$ | 0 / 0 / 1 / 1 | 0 / 1 / 0 / 1 | 0 / 1 / 1 / 0 | $A\overline{B} + \overline{A}B$ (Modulo-2 Addition) |
| XNOR | $Y = \overline{A \oplus B}$ | 0 / 0 / 1 / 1 | 0 / 1 / 0 / 1 | 1 / 0 / 0 / 1 | Equivalence / $AB + \overline{A}\overline{B}$ |
For deeper theoretical proofs and Huntington's postulates that govern these identities, refer to the digital logic chapter on All About Circuits.
Edge Cases: "Don't Care" States and Floating Inputs
Just as thermal derating rows modify base ampacity in electrical wire tables, specific conditions modify the base boolean output in logic synthesis. Understanding how these "derating" equivalents alter your table is critical for preventing erratic circuit behavior.
1. "Don't Care" (X) Conditions in Karnaugh Maps
When simplifying a boolean algebra table using a Karnaugh map (K-map), you will frequently encounter input combinations that can never occur in practice (e.g., invalid BCD states like 1010 through 1111). In the truth table, these outputs are marked with an X (Don't Care). During logic minimization, you can treat the 'X' as either a 1 or a 0—whichever allows you to draw the largest possible grouping loop. This modifies the final simplified boolean expression without violating the physical constraints of the system.
2. Floating Inputs and Internal Pull-Ups
A truth table assumes inputs are firmly driven to a valid logic high or low. If you leave an input pin unconnected (floating) on a CMOS IC like the CD4011 NAND gate, the input impedance is so high that ambient electromagnetic noise will cause the gate to oscillate rapidly between 0 and 1. This violates the boolean table entirely, causing massive $I_{CC}$ current spikes that can overheat and destroy the silicon. Always tie unused CMOS inputs to VCC or GND. Conversely, older TTL ICs (like the 74LS00) have internal pull-up networks that cause a floating input to default to a logic '1', effectively modifying the 'A' or 'B' column of your truth table to a permanent 1.
What the Table Cannot Tell You (Timing and Power)
The boolean algebra table is a purely mathematical construct representing steady-state DC conditions. It is blind to the physical realities of electron mobility and parasitic capacitance. Here is what the table cannot tell you:
- Propagation Delay ($t_{pd}$): The table shows that an AND gate outputs a 1 when both inputs are 1. It does not tell you that a 74HC08 at 5V takes approximately 14ns for the output to transition ($t_{PLH}$/$t_{PHL}$), while at 2V, that same delay stretches to nearly 45ns. In high-speed clocked systems, ignoring propagation delay leads to race conditions and metastability.
- Fan-Out Limits: The table assumes an output can drive infinite subsequent inputs. In reality, a standard 74LS TTL output can only source 400µA and sink 8mA. Exceeding the fan-out limit causes the output voltage to sag below the $V_{IH}$ threshold of the receiving gates, collapsing the logic '1' into an undefined state.
- Setup and Hold Times: For sequential logic (flip-flops, latches), a simple truth table is insufficient. You must consult the component's timing diagram to ensure data inputs are stable for nanoseconds before ($t_{setup}$) and after ($t_{hold}$) the clock edge.
- Power Dissipation: The table does not differentiate between a gate drawing 1µW (CMOS) and a gate drawing 10mW (ECL). For battery-operated embedded systems, the boolean implementation you choose directly dictates your thermal envelope and battery life.
Boolean Algebra Table FAQ
How do I simplify a boolean algebra table using Karnaugh maps?
To simplify a truth table, transfer the '1' outputs from the boolean algebra table into a Karnaugh map grid. Group adjacent '1's into rectangles containing $2^n$ cells (1, 2, 4, 8, etc.). The goal is to cover all '1's with the fewest, largest possible groups. Variables that change state within a group are eliminated, leaving only the variables that remain constant. This yields a minimized Sum of Products (SOP) expression, reducing the physical IC count required on your PCB.
Why does my physical circuit ignore the boolean algebra table outputs?
If your breadboard circuit defies the truth table, you are likely experiencing one of three physical layer failures: (1) Floating inputs causing oscillation, as detailed above; (2) Ground bounce, where high-speed simultaneous switching of multiple outputs causes the local ground reference to spike, falsely triggering logic thresholds; or (3) VCC sag due to insufficient decoupling capacitors. Always place a 100nF (0.1µF) ceramic bypass capacitor as close to the VCC and GND pins of every logic IC as physically possible to maintain stable threshold voltages.
What is the difference between a truth table and a state table?
A boolean algebra truth table applies strictly to combinational logic (AND, OR, XOR), where the output depends solely on the present inputs. A state table (or characteristic table) is used for sequential logic (D flip-flops, JK flip-flops, state machines). A state table includes columns for the "Present State" and the "Next State," acknowledging that the output depends on both the current inputs and the historical memory stored in the circuit's previous clock cycle. You cannot model a microprocessor or a counter using only a basic boolean truth table.
