The baseline resistance of a standard PT100 RTD (Resistance Temperature Detector) at room temperature (25°C / 77°F) is exactly 109.71 Ω, while a PT1000 reads 1097.1 Ω. In power electronics thermal management, knowing this exact baseline is critical. If your microcontroller ADC isn't calibrated to the precise room-temperature resistance before you calculate junction-to-ambient thermal resistance ($R_{\theta JA}$) and select a heatsink, your thermal shutdown loop will either trigger nuisance faults or fail to protect the silicon from catastrophic overheating.
This guide walks through the exact math for sizing a heatsink, interpreting derating curves, and using an RTD to close the thermal monitoring loop.
RTD Baseline: Why Room Temperature Resistance Dictates Calibration
RTDs operate on the principle that the electrical resistance of platinum changes predictably with temperature, governed by the Callendar-Van Dusen equation. Before you mount a sensor to a power stage, you must verify its baseline at a known ambient point—usually 25°C room temperature.
| Temperature (°C) | PT100 (Ω) | PT1000 (Ω) | Common Use Case |
|---|---|---|---|
| 0°C (Ice Point) | 100.00 | 1000.00 | Factory calibration reference |
| 20°C (Standard Ambient) | 107.79 | 1077.94 | HVAC / environmental baseline |
| 25°C (Room Temp) | 109.71 | 1097.13 | Electronics thermal design baseline |
| 50°C | 119.40 | 1194.00 | Typical enclosure ambient limit |
| 100°C (Boiling Point) | 138.51 | 1385.10 | Heatsink thermal throttle threshold |
According to Omega Engineering's RTD reference tables, the alpha coefficient ($\alpha$) for standard platinum is 0.00385 Ω/Ω/°C. If your multimeter reads 112 Ω on a PT100 at a verified 25°C room, your sensor has a 2 Ω offset (likely lead resistance or physical strain) that must be subtracted in firmware before calculating the heatsink delta-T.
Thermal Path Math: Sizing the Heatsink for a 50W MOSFET Load
Let's design a thermal path for a TO-247 packaged N-channel MOSFET (e.g., IXYS IXFH40N60X) dissipating 50W continuous. We will use the thermal resistance network: Junction ($J$) → Case ($C$) → Sink ($S$) → Ambient ($A$).
The Assumptions:
- Max Junction Temp ($T_{J(max)}$): 150°C (Datasheet limit)
- Target Junction Temp ($T_J$): 120°C (20% safety margin for reliability)
- Ambient Temp ($T_A$): 40°C (Inside a ventilated but enclosed chassis)
- Power Dissipation ($P_D$): 50W
Step 1: Calculate Required Total Thermal Resistance ($R_{\theta JA}$)
$$R_{\theta JA} = \frac{T_J - T_A}{P_D} = \frac{120°C - 40°C}{50W} = 1.6 \text{ °C/W}$$
Step 2: Subtract Known Internal Resistances
The MOSFET datasheet specifies a Junction-to-Case resistance ($R_{\theta JC}$) of 0.65 °C/W. We will use a Bergquist Sil-Pad thermal interface material (TIM) which yields a Case-to-Sink resistance ($R_{\theta CS}$) of roughly 0.20 °C/W for a TO-247 package.
$$R_{\theta SA} = R_{\theta JA} - R_{\theta JC} - R_{\theta CS}$$
$$R_{\theta SA} = 1.6 - 0.65 - 0.20 = \mathbf{0.75 \text{ °C/W}}$$
Step 3: Heatsink Selection
A sink-to-ambient ($R_{\theta SA}$) of 0.75 °C/W is impossible to achieve passively without a massive, multi-pound block of aluminum. We must use forced convection. Looking at extruded aluminum profiles, the Aavid Thermalloy 6374BG (a standard 2-inch wide extruded fin profile) has a passive $R_{\theta SA}$ of about 2.8 °C/W. However, when paired with a 40mm fan pushing 15 CFM across the fins, the forced-air derating curve drops its $R_{\theta SA}$ to approximately 0.8 °C/W. This gets us within 6% of our target, keeping $T_J$ at roughly 122°C—well within our safe operating area.
Derating Curves and 'How Hot is Too Hot'
Silicon doesn't instantly die at 151°C, but operating at the absolute maximum junction temperature accelerates failure mechanisms exponentially. So, how hot is too hot?
Interpreting the Derating Curve:
Power device datasheets include a power derating curve. For our MOSFET, it can dissipate 100% of its rated power up to a 25°C case temperature. Above 25°C, the allowable power drops linearly, reaching zero watts at 150°C. If your RTD reads a case temperature of 85°C, the device can only safely dissipate roughly 56% of its maximum rated power. If your control loop doesn't respect this curve, you will exceed the silicon's thermal limits.
Failure Signatures of Thermal Stress:
- Electromigration: High current density combined with temperatures >125°C causes aluminum/copper interconnects inside the die to physically migrate, leading to open circuits.
- Solder Joint Fatigue: Repeated thermal cycling (swinging from 40°C to 120°C) causes the die-attach solder layer to crack due to the coefficient of thermal expansion (CTE) mismatch between silicon and copper. This manifests as a creeping increase in $R_{\theta JC}$ over time.
- Package Delamination: The plastic epoxy encapsulation separates from the leadframe, allowing moisture ingress and subsequent corrosion.
Airflow, Enclosures, and the RTD Decision Tree
What do airflow and enclosure changes actually buy you? Moving from natural convection (passive) to forced convection (a 40mm fan) typically cuts your $R_{\theta SA}$ by 50% to 70%. However, enclosing that fan in a sealed box with inadequate intake/exhaust vents will cause the local ambient temperature ($T_A$) to rise. If $T_A$ rises from 40°C to 60°C because the enclosure traps the exhaust air, your thermal headroom collapses, and the heatsink becomes useless.
Use the following decision matrix to select your RTD topology and cooling method based on your power stage requirements.
| Condition / Power Stage | Cooling Strategy | RTD Topology | ADC Wiring Requirement |
|---|---|---|---|
| $P_D$ < 10W, open bench | Passive stamped heatsink | None required | N/A |
| $P_D$ 10W - 30W, ventilated enclosure | Passive extruded profile | PT100 (2-wire) | Standard Op-Amp circuit |
| $P_D$ 30W - 60W, sealed enclosure | Extruded profile + 40mm fan | PT1000 (2-wire) | Direct to MCU voltage divider |
| $P_D$ > 60W, or high-vibration | Liquid cold plate or massive fin array | PT100 (3-wire or 4-wire) | Dedicated RTD-to-Digital IC (e.g., MAX31865) |
For the vast majority of hobbyist and mid-range industrial power electronics (motor drives, buck converters, audio amplifiers) dissipating between 30W and 60W, the third row is your target. The Analog Devices RTD configuration guide highlights that higher base-resistance sensors drastically simplify the analog front-end.
Final Recommendation: The Default PT1000 Active-Cooling Pick
If you are building a power stage dissipating roughly 50W and need to implement closed-loop thermal throttling, stop evaluating 2-wire PT100 sensors. The 109.71 Ω room temperature baseline of a PT100 is too easily skewed by the 1 Ω of copper trace and wire resistance on your PCB, requiring complex 3-wire compensation or expensive dedicated ICs like the MAX31865.
The Concrete Pick: Use a TE Connectivity NB12L00100K35 (a 2-wire PT1000 probe) epoxied directly to the MOSFET case or zip-tied to the center fin of an Aavid Thermalloy 6374BG extruded heatsink.
Why this terminates the decision:
- Lead Resistance Immunity: At 25°C, the PT1000 reads 1097.1 Ω. A 1 Ω lead wire error introduces less than a 0.25°C measurement offset, which is entirely negligible for thermal throttling logic.
- MCU Compatibility: You can read this PT1000 using a simple 10kΩ pull-up resistor and a standard 12-bit ADC on an ESP32 or STM32, eliminating the need for a $4 dedicated RTD amplifier IC.
- Active Baseline: Pair it with a 40mm x 20mm ball-bearing fan (like the Noctua NF-A4x20) driven by a logic-level MOSFET. Set your firmware to spin the fan at 100% when the PT1000 reads 1242 Ω (approx. 65°C case temp), and aggressively throttle your main PWM duty cycle if the resistance crosses 1347 Ω (approx. 90°C case temp).
By anchoring your thermal design to the exact 1097.1 Ω room-temperature baseline of a PT1000, you eliminate calibration guesswork, simplify your BOM, and ensure your silicon stays safely below the electromigration threshold.
