Converting a 2.5V analog signal using a standard 12-bit AD converter schematic with a 3.3V reference voltage yields a digital output code of 3106. This assumes an ideal linear transfer function where the reference voltage ($V_{ref}$) is exactly 3.300V. If you are using a 5.0V reference with the same 12-bit resolution, that identical 2.5V input shifts to 2048. The core formula substituting these values is: Code = (2.5V / 3.3V) × (2^12 - 1) = 3106. Whether you are designing a precision sensor interface or an AC energy monitor, understanding how your AD converter schematic maps physical voltage to discrete digital units is the foundation of reliable embedded design.

Core AD Converter Schematic Parameters

The numeric answer of any ADC conversion is fixed by three rigid assumptions in your schematic: the Reference Voltage ($V_{ref}$), the Bit Resolution ($n$), and the Architecture Linearity. If your schematic relies on the microcontroller's internal $V_{ref}$ (like the VDD rail), any noise on your 3.3V LDO directly corrupts your conversion. Precision schematics use a dedicated voltage reference IC (like the TI REF3033) to lock this assumption.

Below is the baseline data for common ADC resolutions used in hobbyist and industrial schematics, showing exactly how the Least Significant Bit (LSB) step size shifts between 3.3V and 5.0V logic domains.

Table 1: ADC Resolution, Max Codes, and LSB Step Sizes
Resolution (Bits) Max Digital Code LSB Step @ 3.3V $V_{ref}$ LSB Step @ 5.0V $V_{ref}$ Common IC / MCU Example
8-bit 255 12.94 mV 19.60 mV Arduino Uno (ATmega328P)
10-bit 1023 3.22 mV 4.88 mV Microchip MCP3008
12-bit 4095 0.80 mV 1.22 mV STM32F4 / ESP32 (Internal)
16-bit 65535 0.05 mV (50 µV) 0.07 mV (76 µV) Texas Instruments ADS1115
Schematic Tip: When routing a 16-bit ADC like the ADS1115, a 50 µV step size means that just 1 cm of parallel 5V digital trace can induce enough crosstalk to destroy your lowest bits. Always use a ground plane and keep analog traces away from SPI/I2C clock lines.

Scaling Mains AC: 120V vs 230V vs 3-Phase Schematics

When your AD converter schematic is tasked with measuring AC mains for an energy monitor, you are no longer converting simple DC. You are stepping down high-voltage AC into the safe 0–3.3V window. How the schematic shifts depends entirely on your regional mains voltage and phase configuration.

For a 120V RMS system (North America), the peak voltage is ~170V. A standard resistor divider or a 9V AC-AC wall transformer scaled down to 1.65V RMS (centered at 1.65V DC bias) is sufficient. For 230V RMS systems (EU/UK/AU), the peak is ~325V. Your schematic must double the voltage divider ratio or use a higher-turn-ratio transformer (like the ZMPT101B) to prevent clipping the ADC input. For 3-Phase systems, the schematic requires three completely isolated ADC channels, often utilizing isolated sigma-delta modulators (like the AMC1301) to prevent ground loops across the phases.

If you are calibrating a 12-bit ADC centered around a 2.5V DC bias point for AC sampling, here is how the digital codes map across a ±20% range (2.0V to 3.0V) assuming a 5.0V $V_{ref}$:

Table 2: Neighboring ADC Codes for 2.5V Baseline (±20% Range, 12-bit @ 5V)
Analog Input ($V_{in}$) Deviation from 2.5V Expected 12-bit Code Hex Value
2.00V -20.0% 1638 0x666
2.25V -10.0% 1843 0x733
2.50V Baseline 2048 0x800
2.75V +10.0% 2252 0x8CC
3.00V +20.0% 2457 0x999

When the Conversion is Meaningless

An AD converter schematic will faithfully output a number, but that number can be entirely meaningless if the physical or electrical assumptions are violated. Here are the three most common failure modes where your voltage-to-code conversion falls apart:

  1. Source Impedance Mismatch: Successive Approximation Register (SAR) ADCs use an internal sampling capacitor. If your schematic's source impedance (e.g., a high-value voltage divider) is greater than 10 kΩ, the internal capacitor cannot charge fully during the sampling window. The ADC will report a lower voltage than actually exists. Fix: Add a 100nF decoupling capacitor at the ADC pin or use an op-amp buffer. See Analog Devices' guide on SAR ADC input driving for exact RC filter calculations.
  2. The ESP32 Saturation Cliff: If your schematic uses the internal ESP32 ADC, the conversion becomes non-linear and effectively meaningless above ~2.5V to 2.7V, regardless of the 3.3V $V_{ref}$ assumption. The internal amplifier saturates early. Fix: Use an external I2C ADC like the ADS1115 for any ESP32 project requiring the full 0–3.3V range.
  3. Unknown Power Factor (PF) in AC Mains: When measuring AC power, converting ADC voltage codes and ADC current codes into Real Power (Watts) requires multiplying them instant-by-instant. If your schematic lacks a synchronized voltage sampling channel, or if the phase shift introduced by your current transformer (CT) is uncalibrated, your Power Factor is unknown. In this state, converting ADC codes to Watts is meaningless; you can only calculate Apparent Power (VA).
Warning: Never connect an AD converter directly to mains voltage without an isolation barrier or a properly rated step-down transformer. A failed resistor divider will route 120V/230V AC directly into your microcontroller's GPIO, destroying the silicon and creating a severe shock hazard.

Frequently Asked Questions

Do I need a decoupling capacitor on the $V_{ref}$ pin of my ADC schematic?
Yes. A 10µF tantalum in parallel with a 100nF ceramic capacitor placed within 2mm of the $V_{ref}$ pin is mandatory for 12-bit and higher ADCs. Without it, digital switching noise inside the IC will modulate the reference voltage, causing random code scattering.

Why does my ADC read 4095 when the input pin is disconnected?
A floating ADC pin acts as an antenna, picking up ambient electromagnetic interference. The internal sample-and-hold circuit will charge to the rail. Always use a 10kΩ pull-down resistor to ground on unused ADC channels in your schematic.

Where can I find reliable open-source schematics for AC mains ADC scaling?
The OpenEnergyMonitor project provides extensively tested, open-hardware schematics for safely stepping down 120V and 230V AC for ADC sampling, including bias networks and burden resistor calculations for current transformers.