Binary table numbers represent two distinct but inseparable concepts in electronics: the abstract mathematical weight of each bit position in a digital word, and the physical voltage thresholds that hardware uses to interpret those bits as a logic '0' or '1'. While software engineers treat binary as pure math, hardware builders must bridge the gap between a 1 in code and a 3.3V or 5V electrical signal on a breadboard. This reference provides the exact bit weights for quick conversions, followed by the physical voltage thresholds for the most common logic families used in DIY and prototyping environments.
The Math: Binary Bit Weights and Base Conversions
The table below maps the first 16 binary table numbers (4-bit nibbles) alongside their 8-bit extended weights. This is the foundational lookup for calculating analog-to-digital converter (ADC) resolutions, pulse-width modulation (PWM) duty cycles, and bitwise masking.
0x0F). Source Standard: IEC 60027-2 (Letter symbols to be used in electrical technology - Binary prefixes and numbering).
| Decimal | Hex (4-bit) | Binary (8-bit) | Bit Weight ($2^n$) | Common Use Case |
|---|---|---|---|---|
| 0 | 0x0 | 0000 0000 | 1 ($2^0$) | Logic LOW / Clear register |
| 1 | 0x1 | 0000 0001 | 2 ($2^1$) | Bitwise shift test |
| 3 | 0x3 | 0000 0011 | 4 ($2^2$) | I2C address masking |
| 7 | 0x7 | 0000 0111 | 8 ($2^3$) | SPI clock divider |
| 15 | 0xF | 0000 1111 | 16 ($2^4$) | Lower nibble mask (0x0F) |
| 127 | 0x7F | 0111 1111 | 128 ($2^7$) | Max positive 8-bit signed int |
| 128 | 0x80 | 1000 0000 | 256 ($2^8$) | MSB set / Sign bit trigger |
| 255 | 0xFF | 1111 1111 | 512 ($2^9$) | Max 8-bit unsigned / 100% PWM |
Bookmark Quick-Jumps: If you are configuring an 8-bit timer, 0xFF (255) is your maximum count. If you are extracting the lower 4 bits of a sensor reading via an I2C bus, your bitwise AND mask is 0x0F (15). For 10-bit ADCs (like the default Arduino Uno analogRead), the maximum binary table number is 0x3FF (1023).
The Physics: Logic Family Voltage Thresholds
A '1' in your binary table is meaningless to a physical chip unless it meets the minimum voltage requirement. The following comparison table defines the exact voltage thresholds for the most common logic families encountered in embedded systems and breadboard prototyping.
| Logic Family | Nominal $V_{CC}$ | $V_{IL}$ (Max LOW) | $V_{IH}$ (Min HIGH) | Noise Margin |
|---|---|---|---|---|
| 74LS (TTL) | 5.0V | 0.8V | 2.0V | 0.4V / 0.7V |
| 74HC (CMOS 5V) | 5.0V | 1.35V | 3.15V | 1.35V / 1.35V |
| CD4000 (CMOS) | 5.0V - 15V | 1.5V (at 5V) | 3.5V (at 5V) | Variable by VCC |
| 74LVC (CMOS 3.3V) | 3.3V | 0.8V | 2.0V | 0.5V / 0.4V |
Sources: Texas Instruments SN74HC00 Datasheet; Texas Instruments SN74LVC00 Datasheet.
Which Column Applies to Your Installation?
Match the logic family column to your microcontroller's I/O voltage, not just the chip's absolute maximum ratings. If you are wiring an ESP32 or Raspberry Pi (3.3V logic), you must use the 74LVC / 3.3V CMOS column. Feeding 5V 74HC outputs directly into an ESP32 GPIO will permanently destroy the silicon's ESD protection diodes. If you are using an Arduino Uno (ATmega328P at 5V), use the 74HC column. Avoid 74LS for new designs; its asymmetric noise margins and high power draw make it obsolete for modern low-power battery builds.
How Derating Modifies Base Values
Logic thresholds are not static. The rows in the voltage table above assume a pristine, regulated $V_{CC}$. In reality, power supply sag and thermal derating shrink your noise margins. For example, the 74HC family specifies $V_{IH}$ (minimum voltage to guarantee a HIGH) at 3.15V assuming a 4.5V $V_{CC}$. If your USB power rail sags to 4.2V under a heavy LED load, the actual $V_{IH}$ threshold drops proportionally (CMOS thresholds scale at roughly $0.7 \times V_{CC}$). This means a noisy 2.8V signal that would normally be rejected as a LOW might now falsely register as a logic HIGH, causing ghost inputs on your shift registers.
What Binary Tables Cannot Tell You: Hardware Limits
While binary table numbers and voltage thresholds guarantee logical interpretation, they completely ignore timing, drive strength, and signal integrity. Relying solely on logic voltage tables will lead to failed builds if you ignore these three physical realities:
- Fan-Out and Drive Current ($I_{OL}$ / $I_{OH}$): A logic HIGH might measure 4.9V on your multimeter, but that voltage will collapse if you try to pull too much current. A standard 74HC output can source or sink about 25mA absolute maximum (recommended 6mA). If you connect three standard LEDs (20mA each) directly to a single 74HC595 shift register output, the binary '1' will droop below the $V_{IH}$ threshold of the next chip in the daisy chain, and the internal silicon will overheat. Always use a transistor or ULN2803 Darlington array for loads exceeding 10mA.
- Propagation Delay ($t_{pd}$): Binary tables assume instantaneous state changes. In reality, a 74HC00 NAND gate takes roughly 15 nanoseconds to transition from LOW to HIGH at 5V. At 3.3V, this delay increases to nearly 25ns. If you are clocking a high-speed SPI bus at 20 MHz, these nanosecond delays accumulate across daisy-chained logic gates, eventually shifting the binary data out of phase with the clock edge and causing corrupted bytes.
- Transmission Line Effects: Voltage thresholds assume short, point-to-point breadboard jumps. If you run a 5V binary clock signal over a 2-meter unshielded ribbon cable, the wire's parasitic capacitance and inductance will cause signal ringing. The voltage waveform will overshoot and undershoot the $V_{IL}$ and $V_{IH}$ thresholds multiple times per edge, causing the receiving microcontroller to read a single binary '1' as three rapid-fire clock pulses. For runs over 30cm, you must implement series termination resistors (typically 22Ω to 33Ω) at the source pin to dampen reflections.
Mastering binary table numbers requires treating them as both a mathematical map and a physical specification. Use the bit-weight tables to structure your firmware logic, but always validate your hardware against the specific voltage thresholds, derating curves, and drive limits of your chosen logic family.
