When you need to wire a circuit breaker for a 24V DC LiFePO4 battery bus, standard mechanical thermal-magnetic breakers are often too slow to protect sensitive electronics. A dead short on a low-impedance lithium bank can push thousands of amps in milliseconds, vaporizing PCB traces before a mechanical bimetallic strip has time to heat up and trip. The solution is to design and wire a solid-state electronic circuit breaker (eFuse) that detects overcurrent via a shunt resistor and cuts the gate drive to a MOSFET in under 10 microseconds.
Why Solid-State Over Mechanical for DC Buses?
Mechanical breakers like the popular Blue Sea 187-series rely on thermal bending or magnetic solenoids. Under a massive 1000A fault current, a 30A mechanical breaker might take 10ms to 50ms to open. In a 24V system, that delay allows immense I²t (thermal energy) to pass through the wiring.
Solid-state breakers, utilizing eFuse topologies, monitor the voltage drop across a precision shunt resistor. When the drop exceeds the threshold, an op-amp instantly pulls the gate voltage off the pass-transistor. The trip time is limited only by the op-amp's slew rate and the MOSFET's gate capacitance—typically 2µs to 5µs. This clamps the let-through current to a fraction of what a mechanical breaker allows, saving your inverter's input capacitors and your BMS shunt.
Topology Description & Node Map
We are using a High-Side P-Channel MOSFET Topology. High-side switching is mandatory for DC buses so the load returns to a common, uninterrupted ground plane, preventing ground-loop noise and ensuring the load is fully de-energized (not just floating) when tripped.
Node Labels
- V_IN: 24V DC from the battery busbar (positive).
- V_OUT: Switched 24V DC to the load.
- GND: Common system ground (Battery negative).
- V_SENSE: The measurement node across the shunt resistor.
- V_REF: The fixed trip-point reference voltage.
- V_GATE: The drive node connecting the op-amp output to the MOSFET gate.
Current flows from V_IN, through the P-Channel MOSFET (Q1), through the shunt resistor (R_SENSE), and out to V_OUT. The op-amp (U1) continuously compares V_SENSE to V_REF. If V_SENSE exceeds V_REF, U1's output swings high, pushing V_GATE to the source voltage, turning off Q1.
Design Walkthrough: Picking Real Component Values
Let's design this for a 15A continuous load with a trip point of 18A on a 24V nominal (28.8V max) LiFePO4 bus.
1. The Shunt Resistor (R_SENSE)
We want a manageable voltage drop at the 18A trip point. Let's target a 90mV drop.
R = V / I = 0.090V / 18A = 0.005Ω (5 milliohms).
At 15A continuous, the power dissipation is P = I²R = 225 * 0.005 = 1.125W. We will select a Bourns CSS 0.005Ω 5W surface-mount shunt to handle the heat without drifting.
2. The Pass Transistor (Q1)
We need a P-Channel MOSFET rated for at least -40V Vds and >20A Id, with a low Rds(on) to minimize heat. The IRF4905 (Vds = -55V, Id = -74A, Rds(on) = 20mΩ) is a bench favorite. At 15A, it will dissipate P = 225 * 0.020 = 4.5W. You must mount this to a small TO-220 heatsink; it will get hot without one.
3. The Reference Voltage (V_REF) & Op-Amp
We need V_REF to be exactly 90mV. Using an LM358 op-amp powered from a 5V LDO, we create a voltage divider. Using a 55kΩ and 1kΩ resistor from the 5V rail yields: 5V * (1000 / 56000) = 89.2mV. This is our trip threshold.
Topology Behavior Under Fault Conditions
| Condition | V_SENSE vs V_REF | Op-Amp Output (V_GATE) | MOSFET State |
|---|---|---|---|
| Normal (10A Load) | 50mV < 89.2mV | Low (Near GND) | Fully ON (Conducting) |
| Overload (19A Load) | 95mV > 89.2mV | Swings High (to V_IN) | Turns OFF (< 5µs) |
| Dead Short (0Ω) | Spikes > 89.2mV instantly | Swings High (Slew limited) | Turns OFF (Clamps I²t) |
| Sense Wire Open | Floats (Pulled High by R_pull) | Swings High | Turns OFF (Fail-Safe) |
How to Breadboard-Test the Logic Step-by-Step
You cannot push 15A through a standard solderless breadboard; the internal phosphor-bronze clips will melt. Instead, we breadboard the control logic using a scaled-down proxy load to verify the trip threshold and speed before soldering the high-power FET and shunt to a PCB.
- Wire the Logic: Insert the LM358. Connect Pin 8 to 12V, Pin 4 to GND. Build the V_REF voltage divider on the non-inverting input (Pin 3) of U1A.
- Wire the Proxy Shunt: Place the 0.1Ω resistor in series with your 10Ω dummy load. Connect the high side of the shunt to the inverting input (Pin 2) of U1A.
- Connect the Gate Drive: Wire the op-amp output (Pin 1) through a 100Ω gate-stopper resistor to the gate of a small-signal P-Channel MOSFET (like a 2N7000 proxy or a small logic-level P-FET).
- Verify Normal State: Power the 12V rail. Measure V_OUT with a multimeter. It should read ~11.8V (accounting for the small shunt drop). The op-amp output should be near 0V.
- Inject a Fault: To simulate an overcurrent, temporarily swap the 10Ω load for a 4Ω load (drawing ~3A, generating 300mV across the proxy shunt). The op-amp output should instantly snap to 12V, and V_OUT should drop to 0V.
- Measure Trip Speed: Connect an oscilloscope probe to V_OUT. Trigger on the falling edge when switching from the 10Ω to the 4Ω load. You should see the voltage collapse in under 5µs, confirming the logic is fast enough to protect a real bus.
What Breaks at the Extremes (Failure Modes)
Designing a breaker means designing for its failure. Here is what happens at the electrical extremes:
The Dead Short Extreme (V_OUT to GND)
If the load shorts, current attempts to spike to hundreds of amps. The shunt voltage spikes, and the op-amp turns off the MOSFET in ~3µs. However, for those 3µs, the MOSFET is in the linear region, absorbing massive energy. If your wiring inductance causes a voltage ring, the Vds spike might exceed the IRF4905's -55V rating. The Fix: Always place a 36V bidirectional TVS diode (e.g., SMAJ36CA) directly across the MOSFET's Source and Drain to clamp inductive kickback.
The Open Sense Wire Extreme
If the thin trace connecting the shunt to the op-amp's inverting input breaks or vibrates loose, the input floats. If it floats low, the op-amp thinks current is zero and keeps the breaker closed during a fault. The Fix: Add a 100kΩ pull-up resistor from the inverting input to V_IN. If the sense wire breaks, the input is pulled high, the op-amp sees a massive 'overcurrent', and trips the breaker open. This makes the design fail-safe.
Decision Matrix: Which Breaker Topology to Wire?
Do not default to a solid-state breaker for every application. Use this decision path to select the right protection for your specific branch circuit.
| If your application is... | Then wire this... | Concrete Part Pick |
|---|---|---|
| Main battery feed (>50A), high surge tolerance needed, infrequent faults. | Mechanical Magnetic-Hydraulic Breaker | Blue Sea 187-Series 100A |
| Low current logic bus (<2A), protecting microcontrollers or sensors. | Resettable PTC Polyfuse | Littelfuse 1206L050YR |
| Inverter feed or sensitive BMS bus (5A - 30A), requires <10µs trip to save silicon. | Solid-State P-Channel eFuse (This Design) | IRF4905 + LM358 + 0.005Ω Shunt |
The Verdict: If you are wiring a 15A to 30A branch circuit feeding a sensitive 24V DC/DC converter or an inverter's logic board, wire the solid-state P-Channel topology detailed above. The 4.5W thermal penalty on the IRF4905 is a negligible tradeoff for the microsecond-level let-through current clamping that will prevent a $2,000 inverter from dying during a downstream short circuit. For the main battery trunk, stick to a mechanical Class T fuse or hydraulic breaker to handle the massive inrush currents without nuisance tripping.
