What Is an Arc Fault Circuit Interrupter? Inside the DSP Topology & ESP32 Simulator

What Is an Arc Fault Circuit Interrupter (and How Does Its Embedded Brain Work?)

An arc fault circuit interrupter (AFCI) is a specialized electrical breaker designed to detect the unique, high-frequency electrical noise generated by arcing faults—sparks caused by damaged, loose, or pinched wires—and trip the circuit before a fire can start. While standard thermal-magnetic breakers only react to overcurrent (overloads) and dead shorts, they are completely blind to the low-current, high-impedance series arcs that cause roughly 30,000 residential fires annually in the US.

Under NEC Article 210.12, AFCI protection is mandatory for nearly all 120V, 15A and 20A branch circuits in residential living spaces. But from an embedded systems perspective, an AFCI is essentially a high-speed data acquisition system. Early generations relied on analog bandpass filters, but modern combination-type AFCIs utilize a microcontroller or Digital Signal Processor (DSP) sampling the current waveform at 100 kHz or higher. The firmware performs Fast Fourier Transforms (FFT) and pattern recognition to distinguish the chaotic, broadband RF signature of a carbonizing arc from the normal commutation noise of a vacuum cleaner motor.

Inside the AFCI: The DSP Topology and Node Labels

To understand how an AFCI makes its trip/no-trip decision, we must look at the analog front-end (AFE) topology that feeds the microcontroller. The standard modern topology relies on a current transformer (CT) coupled with a precision operational amplifier stage.

• Node A (Primary Conductor): The 120V AC line/load wire passing through the CT core.
• Node B (CT Secondary): The low-voltage AC current output from the transformer, proportional to the load current.
• Node C (Burden & Bias Network): A low-ohm resistor converting the CT current to voltage, biased at VCC/2 to allow bipolar AC swing on a single-supply MCU.
• Node D (AFE Output / ADC Input): The filtered, buffered signal entering the DSP’s internal ADC.

Why This Topology Over the Alternative?

The alternative to this DSP-driven CT topology is a purely analog high-frequency bandpass filter feeding a comparator. We reject the analog alternative because it suffers from severe component drift over temperature and time. More importantly, an analog filter cannot dynamically adjust its thresholds. A DSP topology allows the manufacturer to push firmware updates and use machine-learning classifiers to differentiate between a harmless switching power supply and a dangerous series arc, drastically reducing nuisance trips.

Behavior Matrix: Component Shifts and Failure Extremes

When designing or troubleshooting the sensor front-end of an arc detection system, component tolerances dictate the signal integrity at Node D. Below is a behavior table detailing what happens when elements shift, followed by the catastrophic extremes.

What Breaks at the Extremes?

Open Circuit at Node B (Open CT Secondary): This is a致命 (fatal) failure mode. If the CT secondary opens while primary current (Node A) is flowing, the transformer core saturates and induces a massive high-voltage spike (often >1000V) across the secondary. This will instantly punch through the AFE op-amp’s input stage, destroy the MCU’s ADC pin, and potentially cause the very fire the IEEE 1699 AFCI standard is meant to prevent.

Short Circuit at Node B (Shorted CT Secondary): The voltage at Node C drops to zero. The DSP receives a flatline at Node D. The breaker becomes completely blind to arc faults and will fail to trip during a real fire hazard, though it will still function as a standard thermal overload breaker.

Breadboard Design Walkthrough: ESP32 Arc Signature Simulator

We cannot safely breadboard a 120V mains AFCI on the bench. However, we can build the exact sensor front-end topology used inside commercial AFCIs and use an ESP32 to sample and analyze the high-frequency noise signature. This simulator allows you to inject "arc noise" (using a piezo igniter or a universal motor) and watch the DSP variance calculations in real-time.

Bill of Materials

• ESP32-WROOM-32 DevKit v1
• SCT-013-000 (100A:50mA) Current Transformer
• MCP6001-I/P (Rail-to-rail op-amp, 3.3V compatible)
• Two 10kΩ 1% resistors (Voltage divider)
• One 100Ω 1% burden resistor
• One 10µF electrolytic capacitor (Bias filtering)
• One 100nF ceramic capacitor (Anti-aliasing filter)

Step-by-Step Breadboard Assembly

1. Establish the Virtual Ground: Wire the two 10kΩ resistors in series between the ESP32 3V3 pin and GND. Connect the 10µF capacitor from the midpoint to GND. This creates a stable 1.65V DC bias at Node C.
2. Wire the CT Secondary: Connect the SCT-013-000 3.5mm jack sleeve and tip across the 100Ω burden resistor. This converts the induced current into a measurable voltage.
3. Configure the Buffer: Feed the 1.65V bias into the non-inverting input (+) of the MCP6001. Connect the CT/burden junction to the same pin via a 1kΩ current-limiting resistor. Wire the op-amp output to its inverting input (-) to create a unity-gain buffer.
4. Apply Anti-Aliasing: Route the op-amp output through a 1kΩ series resistor and the 100nF capacitor to GND. The junction of this RC network is Node D. Wire Node D to ESP32 GPIO 34 (ADC1_CH6).
5. Power the AFE: Connect the MCP6001 VDD to the ESP32 3V3 pin and VSS to GND.

ESP32 DSP Firmware

Real AFCIs sample at >100kHz using I2S peripherals. The ESP32 Arduino `analogRead` function maxes out around 15kHz, which is sufficient to capture the lower harmonics of an arc signature for our bench simulator. The code below calculates the statistical variance of the ADC readings; a sudden spike in variance indicates broadband high-frequency noise (an arc).

#define ADC_PIN 34
#define SAMPLES 1000
#define BASELINE_OFFSET 1898 // Approx 1.65V at 12-bit resolution

void setup() {
  Serial.begin(115200);
  analogSetPinAttenuation(ADC_PIN, ADC_11db);
  Serial.println("AFCI Front-End Simulator Initialized.");
}

void loop() {
  long sum_sq = 0;
  int raw;
  
  // High-speed sampling block
  for(int i = 0; i < SAMPLES; i++){
    raw = analogRead(ADC_PIN);
    long diff = raw - BASELINE_OFFSET;
    sum_sq += (diff * diff);
  }
  
  // Variance acts as our high-frequency noise detector
  double variance = (double)sum_sq / SAMPLES;
  
  Serial.print("Noise Variance: ");
  Serial.println(variance, 2);
  
  // Threshold logic (calibrate based on your specific CT and motor noise)
  if(variance > 50000.0) {
    Serial.println("[TRIP] Arc Fault Signature Detected!");
  }
  
  delay(50);
}

Testing: Clamp the SCT-013 around a wire powering a universal motor (like a drill or blender). Run the code. You will see a baseline variance. Now, use a piezo sparker near the sensor or introduce a loose connection in a low-voltage test loop to inject broadband RF noise. The variance will spike, triggering the simulated trip.

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