A truth table is a mathematical matrix used in digital logic to map every possible combination of binary inputs to their corresponding output states. If you are designing a circuit, programming an FPGA, or troubleshooting a 7400-series logic board, the truth table is your primary reference chart. It tells you exactly what a logic gate, flip-flop, or multiplexer will output (HIGH/1 or LOW/0) for any given set of inputs.
While the concept is simple on paper, real-world bench experience reveals that ideal truth tables rarely tell the whole story. Below is the complete reference data for standard logic gates, followed by the physical realities—like floating CMOS inputs and propagation delays—that dictate how these tables actually behave on your workbench.
The Core Logic Gate Truth Tables (Reference Charts)
The following master table covers the standard 2-input logic functions. The output states are defined by the Texas Instruments SN74HC family datasheets and conform to standard IEEE/ANSI logic definitions. Bookmark this section for quick lookups when wiring basic DIP logic ICs like the 74HC08 (AND), 74HC00 (NAND), or 74HC32 (OR).
| Input A | Input B | AND | NAND | OR | NOR | XOR | XNOR |
|---|---|---|---|---|---|---|---|
| 0 (LOW) | 0 (LOW) | 0 | 1 | 0 | 1 | 0 | 1 |
| 0 (LOW) | 1 (HIGH) | 0 | 1 | 1 | 0 | 1 | 0 |
| 1 (HIGH) | 0 (LOW) | 0 | 1 | 1 | 0 | 1 | 0 |
| 1 (HIGH) | 1 (HIGH) | 1 | 0 | 1 | 0 | 0 | 1 |
Which Output Column Applies to Your Installation?
Not all output columns behave identically in hardware. The table above assumes standard push-pull outputs (like the 74HC08), which actively drive the output pin to either VCC or GND. If you are using an IC with open-drain or open-collector outputs (like the 74HC03 NAND gate), the '0' state actively pulls the line to GND, but the '1' state leaves the pin floating (High-Z). In open-drain installations, you must add an external pull-up resistor (typically 4.7kΩ to 10kΩ) to the VCC rail to achieve the '1' state shown in the table.
How Override Pins and 'Don't Care' States Modify the Base Value
In wire sizing, temperature derating reduces a conductor's base ampacity. In digital logic, control pins and 'Don't Care' (X) states modify the base truth table output. A basic 2-input gate is straightforward, but complex ICs feature enable pins that override the standard data inputs.
Take the 74HC151 8-input multiplexer. Its truth table includes an Enable pin (often labeled E or S). If the Enable pin is held HIGH, the output is forced LOW regardless of what the 8 data inputs or 3 select lines are doing. This is the logic equivalent of a derating factor: the base data truth table is nullified by a global control state.
The Danger of Floating CMOS Inputs
A common mistake hobbyists make is assuming an unconnected input pin defaults to a '0' (LOW) state in the truth table. In older TTL logic (like the 74LS series), unconnected pins internally float HIGH. However, in modern CMOS logic (74HC, CD4000 series), an unconnected input sits in a high-impedance state. It will pick up ambient electromagnetic noise, rapidly oscillating between 0 and 1.
This causes the internal MOSFETs to switch continuously, drawing massive amounts of current and overheating the IC. Always tie unused CMOS inputs to VCC or GND using a 10kΩ resistor, or tie them directly to a known logic level. Never leave them floating.
What the Truth Table Cannot Tell You (Real-World Limits)
A truth table is a static, idealized snapshot. It assumes infinite speed and perfect voltage thresholds. When you move from a textbook simulation to a physical breadboard, you must consult the datasheet for the parameters the truth table hides.
| Parameter | What It Means | Real-World Example (74HC08 at 5V) |
|---|---|---|
| Propagation Delay ($t_{pd}$) | The time it takes for a change at the input to reflect at the output. | ~14 nanoseconds. Cascading 5 gates adds 70ns of delay, which can cause race conditions in high-speed clocks. |
| Input Voltage Thresholds ($V_{IH}$ / $V_{IL}$) | The exact analog voltage required for the IC to register a '1' or '0'. | For a 4.5V supply, $V_{IH}$ (minimum HIGH) is 3.15V. A 2.5V signal will be read as invalid or LOW, not HIGH. |
| Fan-Out Limits | How many input pins a single output pin can reliably drive. | CMOS inputs draw almost zero static current, allowing a fan-out of 50+. TTL fan-out is typically limited to 10. |
| Setup and Hold Times | How long data must be stable before and after a clock edge in flip-flops. | Violating the 5ns setup time on a 74HC74 D-Flip-Flop causes metastability (unpredictable output states). |
Quick-Jump Reference: 3-Input Gates and SR Latches
For more complex builds, 2-input gates aren't enough. Below are the bookmark-friendly quick-jump rows for the most queried 3-input and memory-element truth tables, based on Nexperia 74HC11 and standard SR latch architectures.
3-Input AND / NAND Gates (e.g., 74HC11)
A 3-input gate requires all inputs to be HIGH for an AND output, or any input to be LOW for a NAND output. The full 8-row matrix is condensed here to the critical transition states.
| Input A | Input B | Input C | 3-Input AND | 3-Input NAND |
|---|---|---|---|---|
| 0 | X (Don't Care) | X (Don't Care) | 0 | 1 |
| 1 | 0 | X (Don't Care) | 0 | 1 |
| 1 | 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 1 | 0 |
Note: The 'X' denotes a 'Don't Care' state. In Karnaugh mapping and physical circuit design, if Input A is 0, the output of a 3-input AND gate is guaranteed to be 0, regardless of the physical voltage on B and C.
SR Latch (Set-Reset) Truth Table
Unlike combinational gates, latches have memory. The output depends on both the current inputs and the previous state ($Q_{n-1}$). This table is critical when building debouncing circuits for mechanical switches.
| Set (S) | Reset (R) | Output Q | Output Q' (Not Q) | State Description |
|---|---|---|---|---|
| 0 | 0 | $Q_{n-1}$ | $Q'_{n-1}$ | Hold / No Change (Memory state) |
| 1 | 0 | 1 | 0 | Set (Output forced HIGH) |
| 0 | 1 | 0 | 1 | Reset (Output forced LOW) |
| 1 | 1 | 0* | 0* | Invalid / Forbidden State |
Warning on the Forbidden State: Driving both S and R HIGH simultaneously forces both Q and Q' to the same logic level (0 in a NAND-based latch), breaking the fundamental rule that Q and Q' must be complements. When the inputs return to 0 simultaneously, the resulting state is determined by propagation delay mismatches (a race condition), making the final output entirely unpredictable. Never design a circuit that allows an SR latch to enter the 1,1 state.
For a deeper dive into logic symbols and schematic representations, refer to the comprehensive guides on All About Circuits. Understanding the gap between the idealized truth table and the physical silicon limitations is what separates a theoretical student from a competent electronics builder.
