A half adder is a combinational digital logic circuit that adds two single-bit binary inputs to produce a two-bit output consisting of a Sum and a Carry. While basic logic gates merely route, invert, or mask signals, introducing a half adder changes a circuit's fundamental capability, elevating it from simple boolean decision-making to actual arithmetic computation. It is the absolute bedrock of digital math, forming the least significant bit (LSB) stage of every Arithmetic Logic Unit (ALU) in modern processors.
The Logic: How a Half Adder Actually Works
Under the hood, a half adder is just two standard logic gates operating in parallel on the same two inputs (A and B). The Sum is generated by an Exclusive-OR (XOR) gate, and the Carry is generated by an AND gate.
Let's look at a worked numeric example using real voltage levels on a standard 5V breadboard. Assume Logic 0 is 0V and Logic 1 is 5V. We want to add binary 1 and binary 1.
- Inputs: Pin A receives 5V (Logic 1). Pin B receives 5V (Logic 1).
- Sum Path (XOR): Because both inputs are identical (High/High), the XOR gate outputs 0V (Logic 0).
- Carry Path (AND): Because both inputs are High, the AND gate outputs 5V (Logic 1).
- Result: The Carry is 1, the Sum is 0. Read together as a binary string (Carry then Sum), the output is
10, which is the decimal number 2. The math checks out: 1 + 1 = 2.
| Input A | Input B | Carry (A AND B) | Sum (A XOR B) | Decimal Equivalent |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 + 0 = 0 |
| 0 | 1 | 0 | 1 | 0 + 1 = 1 |
| 1 | 0 | 0 | 1 | 1 + 0 = 1 |
| 1 | 1 | 1 | 0 | 1 + 1 = 2 (Binary 10) |
Half Adder vs. Full Adder: The Common Confusion
The most common mistake hobbyists and students make is confusing the half adder with the full adder. The distinction is purely about the Carry-In pin.
A half adder has two inputs (A and B). A full adder has three inputs (A, B, and Carry-In). Because the half adder lacks a Carry-In, it is physically impossible to cascade multiple half adders together to add multi-bit numbers.
To prove this, let's try to add binary 11 (decimal 3) and 01 (decimal 1) using two half adders.
For the LSB (Bit 0): 1 + 1 = Sum 0, Carry 1.
For the MSB (Bit 1): 1 + 0 = Sum 1, Carry 0.
The combined output reads 10 (decimal 2). But 3 + 1 equals 4 (binary 100). The half adder failed because it dropped the carry generated by the LSB. A full adder solves this by feeding the LSB's carry into the MSB's Carry-In pin, allowing the math to cascade correctly.
Where You Meet This in Practice
You rarely wire discrete half adders on a breadboard for a final product, but the architecture is everywhere in modern electronics:
- Microcontroller ALUs: Inside the STM32 or ATmega328P, the ALU uses a chain of full adders, but the very first stage (the LSB) is often optimized as a half adder to save silicon area, since there is no previous carry to accept.
- FPGA Carry Chains: When you write
A + Bin Verilog for an AMD/Xilinx FPGA, the synthesis tool doesn't use generic Look-Up Tables (LUTs). It maps the addition to dedicated hardware carry-chain logic. The first cell in that chain operates exactly as a half adder. - Digital Clocks and Counters: Simple binary ripple counters use adder logic to increment values on each clock pulse.
Decision Tree: Which Adder Architecture Do You Need?
Don't default to wiring discrete gates unless you are specifically studying logic propagation. Use this decision path to pick the right hardware for your project.
| If your project requires... | Then choose this architecture... | Concrete Part / Implementation |
|---|---|---|
| Adding exactly two 1-bit signals with no prior carries (e.g., a simple parity checker or LSB indicator). | Discrete Half Adder | 74HC86 (XOR) + 74HC08 (AND) |
| Adding multi-bit numbers (4-bit, 8-bit) on a physical breadboard or perfboard. | Dedicated Full Adder IC | SN74HC283 (4-Bit Binary Full Adder) |
| Performing math inside a CPLD or FPGA fabric. | Native HDL Operator | Use the + operator in Verilog/VHDL to infer dedicated silicon carry-chains. |
| High-speed arithmetic (>50 MHz) in a custom PCB design. | Microcontroller / DSP | Offload to an ARM Cortex-M4F (e.g., STM32G4 series) with hardware math accelerators. |
Breadboarding a Discrete Half Adder
If you need to physically build a half adder to visualize the logic or test a custom PCB footprint, here is the exact bill of materials and wiring procedure.
Parts List
- 1x 74HC86 (Quad 2-Input XOR Gate)
- 1x 74HC08 (Quad 2-Input AND Gate)
- 2x Tactile pushbuttons (for Inputs A and B)
- 2x 10kΩ pull-down resistors
- 2x 330Ω current-limiting resistors (for output LEDs)
- 2x 5mm LEDs (Red for Carry, Green for Sum)
- 1x 100nF (0.1µF) ceramic decoupling capacitor
Wiring Procedure
- Power Rails: Connect VCC (Pin 14 on both ICs) to your 5V rail. Connect GND (Pin 7 on both ICs) to ground. Do not skip the 100nF decoupling capacitor across VCC and GND as close to the ICs as possible; HC-series logic draws sharp current spikes during state transitions that will cause phantom switching without it.
- Inputs: Wire Input A to Pin 1 on both the 74HC86 and 74HC08. Wire Input B to Pin 2 on both ICs. Use the 10kΩ pull-down resistors to tie these lines to GND so they read a solid Logic 0 when the buttons are unpressed.
- Sum Output: The XOR result appears on Pin 3 of the 74HC86. Wire this through a 330Ω resistor to your Green LED, then to GND.
- Carry Output: The AND result appears on Pin 3 of the 74HC08. Wire this through a 330Ω resistor to your Red LED, then to GND.
- Unused Gates: Tie the inputs of any unused gates on both chips to GND. Floating inputs on CMOS (HC-series) chips act as antennas, picking up EMI and causing the chip to overheat from rapid internal oscillation.
Frequently Asked Questions
Can I use a half adder to subtract binary numbers?
No. A half adder only performs addition. To perform subtraction, digital systems use a adder combined with a NOT gate to create the two's complement of the subtrahend, effectively turning the addition circuit into a subtractor. You would need a full adder architecture to handle the borrow/carry bits correctly across multiple bits.
Why do we call it a 'half' adder?
It is called 'half' because it is literally half of a full adder. A full adder can be constructed by combining two half adders and an OR gate. The first half adder adds A and B. The second half adder adds that result to the Carry-In. The OR gate combines the carry outputs from both stages.
What is the propagation delay of a discrete half adder?
It depends on your logic family. If you use modern 74HC-series CMOS at 5V, the typical propagation delay ($t_{pd}$) is about 14ns per gate. Because the Sum and Carry paths only pass through one gate each, the total delay from input change to output stabilization is roughly 14ns to 18ns. If you use older 74LS TTL logic, expect delays closer to 20ns-30ns, alongside much higher power consumption.
Should I use 74LS or 74HC chips for breadboarding?
Always default to the 74HC (High-speed CMOS) family for modern bench work. The older 74LS (Low-power Schottky TTL) family requires strict voltage thresholds, draws significantly more quiescent current, and is largely obsolete. 74HC chips operate cleanly from 2V to 6V and interface perfectly with both 5V Arduino GPIOs and 3.3V ESP32 outputs (provided you run the 74HC chips at 3.3V).
