A combinational circuit is a digital logic network where the output state is determined exclusively by the current combination of input states. Unlike sequential circuits, combinational topologies possess no internal memory, no feedback loops, and no clock dependency. The output is a pure, instantaneous mathematical function of the present inputs. If you change an input, the output updates after a brief propagation delay, with zero awareness of what the inputs were a microsecond ago.
To understand this practically, we will design, map, and breadboard a fundamental combinational block: a 2-to-1 Multiplexer (MUX). A MUX acts as a digital switch, routing one of two input signals to a single output based on a select line. We will build this using discrete 74HC-series logic gates rather than a dedicated MUX IC to expose the internal topology and node behavior.
Logic Family Selection: 74HC vs. Alternatives
Before wiring a single jumper, you must select your logic family. For a 5V bench-top combinational design, the 74HC (High-Speed CMOS) family is the modern standard. It offers the speed of older TTL with the power efficiency of CMOS. Below is a data-dense comparison to justify this choice for our topology.
| Logic Family | VCC Range | Typ. Propagation Delay ($t_{pd}$) | Input Impedance | Static Power (per gate) | Best Use Case |
|---|---|---|---|---|---|
| 74HC (CMOS) | 2.0V – 6.0V | ~8 ns @ 5V | Extremely High ($>10^{12} \Omega$) | < 1 µA | General 5V/3.3V combinational logic |
| 74LS (TTL) | 4.75V – 5.25V | ~9 ns @ 5V | Moderate (~20 k$\Omega$) | ~2 mW | Legacy repairs, high-noise environments |
| CD4000B (CMOS) | 3.0V – 15.0V | ~50 ns @ 5V | Extremely High | < 1 µA | High-voltage (12V) battery systems |
| 74LVC (Low-V CMOS) | 1.65V – 3.6V | ~4 ns @ 3.3V | Extremely High | < 1 µA | Modern 3.3V microcontroller interfacing |
Topology and Node Mapping: Building the 2-to-1 MUX
A 2-to-1 MUX requires three inputs: Data Input 0 ($I_0$), Data Input 1 ($I_1$), and a Select line ($S$). The Boolean expression is $Y = (I_0 \cdot \overline{S}) + (I_1 \cdot S)$. To build this, we need one NOT gate, two AND gates, and one OR gate.
Component Bill of Materials (BOM)
- IC1: 74HC04 (Hex Inverter) – Used for $\overline{S}$
- IC2: 74HC08 (Quad 2-Input AND) – Used for the product terms
- IC3: 74HC32 (Quad 2-Input OR) – Used for the final sum
- Decoupling: Three 100nF (0.1µF) X7R ceramic capacitors
Physical Pin and Node Mapping
Here is the exact physical routing on the breadboard. Node labels correspond to the schematic topology.
- Node $S$ (Select): Routed to IC1 Pin 1. Inverted output ($\overline{S}$) emerges at IC1 Pin 2.
- Node $I_0$: Routed to IC2 Pin 1.
- Node $N_1$ (Internal): IC2 Pin 2 receives $\overline{S}$ (from IC1 Pin 2). The AND result ($I_0 \cdot \overline{S}$) emerges at IC2 Pin 3.
- Node $I_1$: Routed to IC2 Pin 4.
- Node $N_2$ (Internal): IC2 Pin 5 receives $S$ (direct from input). The AND result ($I_1 \cdot S$) emerges at IC2 Pin 6.
- Node $Y$ (Output): IC3 Pin 1 receives $N_1$. IC3 Pin 2 receives $N_2$. The final OR result emerges at IC3 Pin 3.
Behavior Table: State Transitions
This table demonstrates the purely combinational nature of the circuit. Notice how the output $Y$ strictly follows the active data line dictated by $S$, with no regard for previous states.
| Select ($S$) | Input 0 ($I_0$) | Input 1 ($I_1$) | Internal $N_1$ | Internal $N_2$ | Output ($Y$) | Behavioral Note |
|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | $I_0$ routed; $I_0$ is LOW |
| 0 | 1 | 0 | 1 | 0 | 1 | $I_0$ routed; $I_0$ is HIGH |
| 0 | 0 | 1 | 0 | 0 | 0 | $I_0$ routed; $I_1$ ignored |
| 0 | 1 | 1 | 1 | 0 | 1 | $I_0$ routed; $I_1$ ignored |
| 1 | 0 | 0 | 0 | 0 | 0 | $I_1$ routed; $I_1$ is LOW |
| 1 | 1 | 0 | 0 | 0 | 0 | $I_1$ routed; $I_0$ ignored |
| 1 | 0 | 1 | 0 | 1 | 1 | $I_1$ routed; $I_1$ is HIGH |
| 1 | 1 | 1 | 0 | 1 | 1 | $I_1$ routed; $I_0$ ignored |
Failure Modes at the Extremes
Combinational circuits built from discrete CMOS gates are highly susceptible to specific physical failure modes that simulation software often hides. Understanding these extremes is critical for bench debugging.
Extreme 1: The Floating Input (Open Circuit)
The Scenario: You forget to connect the Select ($S$) line, leaving IC1 Pin 1 unconnected. What Breaks: Unlike older TTL (74LS), which defaults to a logical HIGH when floating due to internal pull-ups, 74HC CMOS inputs have near-infinite impedance. A floating pin acts as an antenna, picking up ambient electromagnetic noise. The gate will rapidly oscillate between HIGH and LOW. The Result: Both the PMOS and NMOS transistors inside the gate momentarily turn on simultaneously during transitions (shoot-through current). The IC will draw massive current (spiking from µA to tens of mA), overheat, and potentially destroy the silicon. The Fix: Never leave a CMOS input floating. If a gate in the 74HC04 is unused, tie its input directly to GND or VCC.
Extreme 2: Output Short to Ground
The Scenario: A stray wire bridges Node $Y$ (IC3 Pin 3) to the GND rail while $I_1$ and $S$ are both HIGH. What Breaks: The OR gate attempts to drive the output HIGH (VCC), but the short forces it to 0V. The Result: The 74HC32 will attempt to source its maximum short-circuit current (typically ~50mA, though absolute max ratings dictate 25mA per pin). The internal output transistor will thermally runaway and fail open or shorted. The Fix: If you need to drive a low-impedance load (like an LED), always place a current-limiting resistor (e.g., 330$\Omega$ for ~10mA at 5V) in series with the output.
Step-by-Step Breadboard Verification
Do not wire the entire circuit and apply power at once. Use this systematic approach to isolate faults.
- Seat and Power: Place IC1, IC2, and IC3 across the breadboard center trench. Connect VCC (Pin 14) and GND (Pin 7) for all three ICs to the power rails. Set your bench supply to exactly 5.0V.
- Decouple: Insert a 100nF ceramic capacitor across the VCC and GND pins of each IC. Keep the leads as short as possible to minimize parasitic inductance, which can cause high-frequency ringing.
- Tie Off Unused Gates: Ground the inputs of all unused gates on the 74HC04, 74HC08, and 74HC32. This prevents the shoot-through current issue described in the failure modes section.
- Test the Inverter (IC1): Wire the $S$ input. Use a digital multimeter (DMM) in DC Voltage mode. When $S$ is tied to GND, measure IC1 Pin 2 (expect ~5.0V). When $S$ is tied to VCC, measure Pin 2 (expect ~0.0V).
- Test the AND Gates (IC2): Apply 5V to both $I_0$ and $\overline{S}$ (by setting $S$ to GND). Measure IC2 Pin 3 ($N_1$). It must read ~5.0V. Change any input to 0V, and $N_1$ must drop to ~0.0V.
- Test the OR Gate (IC3): Verify that if either $N_1$ or $N_2$ is HIGH, Node $Y$ (IC3 Pin 3) reads ~5.0V. Only when both are 0V should $Y$ read 0.0V.
- Dynamic Test: Replace the manual jumper on $I_0$ with a 1Hz square wave from a function generator (0-5V). Toggle $S$ manually. Observe the output $Y$ on an oscilloscope; it should pass the square wave when $S=0$ and block it (stay LOW) when $S=1$.
Combinational vs. Sequential: Why This Topology?
Why build a combinational MUX instead of using a sequential alternative, like a D-Flip-Flop or a dedicated sequential routing IC? The decision comes down to latency determinism and clock skew.
In a sequential circuit, outputs only update on the rising or falling edge of a clock signal. This introduces setup and hold time requirements, and necessitates a global clock distribution network. If you are routing high-speed asynchronous data—such as an interrupt signal from a sensor to a microcontroller—a sequential latch would bottleneck the signal to the clock frequency and introduce jitter.
A combinational circuit like our 74HC MUX is purely asynchronous. The latency is simply the sum of the propagation delays through the physical silicon. For our topology, the worst-case delay is the path through the inverter, then the AND gate, then the OR gate: $t_{pd(total)} \approx 8ns + 8ns + 8ns = 24ns$. This deterministic, sub-30ns latency is why combinational logic is used for critical address decoding and ALU routing in processor design. For deeper architectural comparisons, All About Circuits provides an excellent breakdown of how these topologies integrate into larger systems.
While dedicated ICs like the 74HC157 Quad 2-Line to 1-Line MUX exist and save breadboard space, building the discrete topology remains the best method for internalizing how Boolean algebra physically manifests as voltage states on a bench.
