A voltage divider using capacitor components (a capacitive divider) scales AC voltages by exploiting capacitive reactance rather than resistance. The output voltage is inversely proportional to the capacitance values: Vout = Vin × [C1 / (C1 + C2)]. Unlike resistive dividers, an ideal capacitive divider dissipates zero real power, making it the standard topology for high-voltage AC step-down applications like mains-sensing circuits and high-impedance signal scaling.
Below, we break down the exact topology, map out the failure modes, and walk through a real-world design for stepping 120VAC down to a microcontroller-safe 5VAC signal.
Topology and Node Definitions
A basic capacitive divider consists of two capacitors in series across an AC source. Because capacitors block DC, this topology only works for alternating current or pulsing signals.
- Node A (Source): The AC input line (e.g., 120VAC Hot).
- Node B (Output): The midpoint between the two capacitors. This is where you measure Vout.
- Node C (Return): The AC neutral or circuit common ground.
The voltage drop across each capacitor is dictated by its capacitive reactance (XC), defined as XC = 1 / (2πfC). Since the same current flows through both series components, the voltage divides inversely to the capacitance. The larger the capacitance, the lower its reactance, and the smaller the voltage drop across it. For a deep dive into the underlying math, refer to the All About Circuits guide on Capacitive Reactance.
Behavior Matrix and Fault Extremes
Before soldering anything, you must understand how this topology reacts to component drift and catastrophic failures. In mains-voltage circuits, a single failed capacitor can expose your low-voltage microcontroller to 120VAC, instantly destroying it and creating a shock hazard.
| Condition / Fault | Effect on Vout | Phase Shift Impact | Real-World Consequence |
|---|---|---|---|
| Increase C1 (Series) | Vout Increases | Phase angle decreases slightly | Output overvoltage; potential ADC clipping. |
| Increase C2 (Shunt) | Vout Decreases | Phase angle increases slightly | Signal drops below ADC noise floor. |
| Increase Frequency | No change (Ideal) | No change | Ratio holds, but total current draw increases. |
| Short C1 | Vout = Vin | Zero shift | Catastrophic: Full mains voltage hits Node B. Destroys downstream ICs. |
| Open C1 | Vout = 0V | N/A | Open circuit. System reads zero; failsafe but blind. |
| Short C2 | Vout = 0V | N/A | Node B shorted to Neutral. Blows upstream fuse if C1 isn't sized to limit current. |
| Open C2 | Vout = Vin | Zero shift | Catastrophic: If measured with high-Z scope, Node B floats to full mains potential. |
Why Capacitive Over Resistive? (The Heat Problem)
Why not just use two resistors? The answer is real power dissipation (heat). Let’s compare stepping 120VAC down to 12VAC to feed a high-impedance op-amp buffer drawing 2mA.
- Resistive Divider: To drop 108V at 2mA, the series resistor must be 54,000Ω. The power dissipated is P = I²R = (0.002)² × 54,000 = 0.216 Watts. While manageable, if you needed 50mA for a small power supply, that same resistor would dissipate 5.4 Watts, requiring a massive, expensive wirewound resistor that gets hot enough to scorch a PCB.
- Capacitive Divider: To achieve the same 54,000Ω reactance at 60Hz, you need a 49nF capacitor. The real power dissipated by an ideal capacitor is 0 Watts. It only stores and releases energy (reactive power). The physical component runs completely cold.
For a comprehensive look at how AC circuits handle reactive vs. real power, see the Electronics Tutorials breakdown of AC capacitance.
Design Walkthrough: 120VAC to 5VAC Signal Dropper
Let’s design a divider to step 120VAC (60Hz) down to ~5VAC for an isolated RMS voltage sensor feeding an ESP32 ADC. We need a high-impedance output.
1. Calculate the Required Ratio:
Target Ratio = Vout / Vin = 5V / 120V = 0.0416
2. Pick C2 (Shunt Capacitor):
We want C2 large enough to provide a stable low-impedance node for the ADC, but small enough to keep total mains leakage current low. Let’s choose 1.0 µF.
Component Spec: 1.0 µF, 275VAC X2-rated metallized polypropylene film capacitor (e.g., EPCOS/TDK B32922 series). Never use standard DC ceramic capacitors for mains shunt duties; they will fail short and cause a fire.
3. Calculate C1 (Series Dropping Capacitor):
Using the formula: Ratio = C1 / (C1 + C2)
0.0416 = C1 / (C1 + 1.0)
0.0416(C1 + 1.0) = C1
0.0416C1 + 0.0416 = C1
0.0416 = 0.9584C1
C1 = 0.0434 µF (43.4 nF)
4. Select Standard Value and Recalculate:
The closest standard E12 value is 47nF.
New Vout = 120V × [47 / (47 + 1000)] = 120V × 0.0448 = 5.38 VAC RMS.
This is well within the safe clamping range of a 5.1V Zener diode placed at Node B.
5. Add the Bleeder Resistor:
When you unplug the device, C1 can retain a lethal 120V charge. To comply with IEC 60384-14 safety guidelines, place a 1MΩ, 0.5W metal film resistor in parallel with C1. This will discharge the capacitor to a safe <50V level within roughly 1 second of disconnect.
How to Breadboard-Test Safely (Step-by-Step)
CRITICAL RULE: Never breadboard raw 120VAC mains. Solderless breadboards are rated for low voltage and low current; mains voltage will arc across the internal spring clips, causing a short, melting the plastic, and creating a severe shock hazard. To verify your divider ratio on the bench, we use a low-voltage AC proxy.
- Set up the Proxy Source: Configure a benchtop function generator to output a 10Vpeak-to-peak (3.53V RMS) sine wave at 60Hz. (If your generator doesn't do 60Hz cleanly, 1kHz is fine, but remember XC scales with frequency, so your physical voltage ratio will only match if both caps are ideal. Stick to 60Hz if possible).
- Scale the Components: To keep the current safe for the breadboard and generator (which usually maxes out at 50mA), scale the capacitors up by 10x. Use a 470nF cap for C1 and a 10µF non-polarized electrolytic or film cap for C2.
- Wire the Topology: Connect the generator's output to Node A. Connect C1 between Node A and Node B. Connect C2 between Node B and the breadboard ground rail (Node C). Connect the generator's ground to Node C.
- Probe Node B: Connect your oscilloscope probe to Node B. Set the scope to AC coupling.
- Verify the Math: You should see a sine wave at Node B with an amplitude of roughly 0.47Vpeak-to-peak (10Vpp × [470 / (470 + 10000)]).
- Test the Extremes: Briefly short C2 with a jumper wire. Verify Vout drops to 0V. Remove the jumper, then lift one leg of C1 (simulating an open). Verify Vout drops to 0V. This confirms your failure-mode logic before you commit the real X2 capacitors to a soldered PCB.
