When a designer or technician asks, "where is the voltage regulator located," they are usually asking two entirely different questions. Topologically, the regulator sits in the power tree between the raw DC bus (rectified AC, battery, or USB VBUS) and the sensitive point-of-load (POL). Physically, its location on the printed circuit board (PCB) is strictly dictated by thermal dissipation limits, high-frequency switching loops, and electromagnetic interference (EMI) constraints.
Placing a regulator in the wrong topological node will destroy your efficiency; placing it in the wrong physical coordinate will cause thermal shutdown or catastrophic analog noise. Below is a comprehensive guide to locating your regulators both on the schematic and on the copper.
Topological Location: The Power Tree & Regulator Selection
In a schematic, the voltage regulator is located immediately after the bulk input protection and filtering stage, and immediately before the decoupling capacitors of the load IC. The choice between a linear regulator (LDO) and a switching regulator (Buck/Boost) at this node depends entirely on your load current, acceptable heat dissipation, and noise tolerance.
Linear vs. switching for a specific load comes down to a strict threshold: if your load draws less than 300mA and requires ultra-low noise (like an RF transceiver or a 16-bit ADC), locate an LDO at the point of load. If your load exceeds 500mA or requires a large step-down ratio (e.g., 12V to 3.3V), you must locate a switching buck converter to prevent silicon-melting heat dissipation.
| Topology | Typical Efficiency | Heat Profile | Output Noise / Ripple | Relative Cost | Best Topological Location |
|---|---|---|---|---|---|
| Linear (LDO) | 30% - 65% | High (burns excess voltage as heat) | Ultra-low (10 - 50 µV RMS) | Low ($0.20 - $0.80) | Final stage before noise-sensitive analog/RF loads |
| Buck (Step-Down) | 85% - 96% | Low (minimal wasted energy) | Moderate (10 - 40 mV p-p switching ripple) | Medium ($0.80 - $2.50) | First stage after raw DC input for high-current digital/motor loads |
| Boost (Step-Up) | 80% - 92% | Low to Moderate | High (continuous diode recovery noise) | Medium ($1.00 - $3.00) | Battery-powered systems needing higher logic rails |
| Buck-Boost | 85% - 94% | Moderate (4-switch losses) | Moderate to High | High ($2.50 - $5.00+) | Wide-input battery systems (e.g., 1S Li-ion to 3.3V) |
For ripple and noise expectations, a modern LDO like the Texas Instruments TPS7A47 will yield less than 20 µV RMS of broadband noise, making it ideal for sensor front-ends. Conversely, a standard 500kHz buck converter will inject 15-30mV of peak-to-peak switching ripple onto the rail, which can easily couple into high-impedance analog traces if not filtered.
Physical PCB Placement: Thermal and Noise Constraints
Once the topology is chosen, the physical location on the PCB must be optimized for either thermal escape (linear) or loop inductance minimization (switching).
Linear Regulator Placement (Thermal Focus)
LDOs dissipate power as heat. If you are using a SOT-223 or TO-252 (DPAK) package, the physical location must prioritize thermal vias. The exposed thermal pad on the bottom of the IC must be soldered to a large internal or bottom-layer ground plane copper pour. You should locate an array of thermal vias (typically 0.3mm diameter, 1.2mm pitch) directly under the pad to wick heat to the opposite side of the board. Never locate an LDO in a dead corner of the board with no airflow or copper pour; it will hit thermal shutdown at half its rated current.
Switching Regulator Placement (EMI and Loop Focus)
Switching regulators (Analog Devices / TI Buck ICs) are governed by high di/dt (change in current over time). The physical location of the input capacitor is critical. The ceramic input capacitor must be placed as physically close as possible to the IC's VIN and PGND (power ground) pins. This minimizes the "hot loop" area, reducing parasitic inductance that causes high-frequency ringing and radiated EMI.
Furthermore, locate the inductor close to the IC's SW (switch) pin, but keep it far away from sensitive analog traces, I2C lines, or crystal oscillators. The inductor radiates a magnetic field; placing it over a high-impedance feedback trace will inject noise directly into the regulator's control loop, causing output jitter.
Design Example: 12V to 5V/3.3V Mixed-Signal Board
Let's apply these location rules to a concrete design. We are building an IoT control board powered by a 12V DC wall wart. The board requires 5V at 1.5A for relays and indicator LEDs, and 3.3V at 300mA for an ESP32-S3 microcontroller.
Input Range and Protection Location
A nominal 12V wall wart can output up to 15V under light loads and is susceptible to inductive spikes when plugged into long DC cables. The protection block must be located at the very edge of the board, immediately after the barrel jack. We place a TVS diode (e.g., SMAJ15A, which clamps at 16.5V) to absorb transients, followed by a P-channel MOSFET (e.g., SI2301) for reverse-polarity protection. This ensures that if the user plugs in a 24V supply by mistake, the TVS clamps and the P-FET remains safely off, protecting downstream regulators.
Stage 1: The 5V Buck Converter
For the 5V rail, we locate a TI TPS5430DDAR buck converter. It accepts inputs from 5.5V to 36V and switches at 500kHz. Because the relays and LEDs are noise-tolerant and draw high current, the switching topology is mandatory here. We place the TPS5430 near the board edge, routing the heavy 5V current directly to the relay coils via 40mil (1mm) traces.
Stage 2: The 3.3V LDO
The ESP32-S3 contains a sensitive RF matching network and a 12-bit ADC that will perform poorly if fed directly from the 500kHz ripple of the TPS5430. Therefore, we locate a TPS7A47 ultra-low-noise LDO topologically after the 5V buck, stepping 5V down to 3.3V.
Headroom and Dropout Math: The TPS7A47 has a maximum dropout voltage of 310mV at 1A. At our 300mA load, the dropout is roughly 90mV. Our available headroom is $5.0V - 3.3V = 1.7V$. Because 1.7V is vastly greater than 90mV, the LDO operates deep in its regulation region, providing excellent Power Supply Rejection Ratio (PSRR) to strip away the buck converter's switching noise. Physically, this LDO is placed within 5mm of the ESP32-S3 VDD pins, with a 1µF X7R ceramic capacitor located directly adjacent to the microcontroller's power pins.
Protection, Headroom, and Real-World Gotchas
Even with perfect topological and physical placement, designers frequently fall victim to component-level non-idealities that alter the effective location of the regulation point.
The MLCC DC Bias Derating Trap
Switching regulators require low-ESR ceramic capacitors (MLCCs) on the input and output. A common mistake is specifying a 10µF, 16V X5R capacitor for the output of a 12V buck converter. Due to DC bias derating, a 16V X5R capacitor subjected to 12V DC will lose up to 60% of its nominal capacitance, effectively acting as a 4µF capacitor. This shifts the regulator's control loop pole, potentially causing phase margin degradation and output ringing. Always locate your capacitor selection in the manufacturer's DC bias curves, or step up to a 25V or 35V rated X7R part to ensure you actually get the 10µF you designed for.
Feedback Resistor Routing (Kelvin Sense)
The physical location of the feedback (FB) trace dictates the actual regulated voltage at the load. If you route the FB trace from the regulator's output pin rather than directly from the load's VDD pin, the voltage drop across the PCB trace resistance ($V = I \times R_{trace}$) will cause the load to see a lower voltage than intended. Always use a Kelvin sense connection: route the FB trace directly from the load's decoupling capacitor, ensuring the regulator compensates for the trace drop.
Ultimately, knowing where the voltage regulator is located means understanding that power supply design is a compromise between thermal reality, magnetic fields, and silicon physics. Map your power tree logically, respect the hot loops on your PCB, and always verify your headroom math before sending the board to fabrication.
