A voltage follower op amp circuit (also known as a unity gain buffer) outputs the exact voltage applied to its non-inverting input (Gain = 1) while transforming a high-impedance source into a low-impedance drive. It provides zero voltage amplification but massive current amplification, solving impedance mismatch issues that would otherwise attenuate your signal.
Topology and Node Behavior
The topology relies on 100% negative feedback. The input signal enters the non-inverting node (+). The output node is tied directly back to the inverting node (-). Because the op-amp's open-loop gain is massive (often >100,000), the internal differential amplifier forces the voltage at the inverting node to match the non-inverting node, creating a 'virtual short' between the two inputs. The output simply follows the input to maintain this equilibrium.
Assuming a standard dual-supply configuration (±15V) at 25°C ambient, here is how a JFET-input op-amp like the TL072 behaves under varying real-world conditions:
| Input Condition (V_in) | Expected V_out | Input Current (I_in) | Phase Shift | Notes / Edge Cases |
|---|---|---|---|---|
| DC 2.5V (Mid-rail) | 2.5V | < 5 pA | 0° | Ideal operation; virtual short maintained. |
| DC 13.5V (Near +15V rail) | 13.5V | < 5 pA | 0° | Approaching common-mode limit; watch for headroom. |
| 10kHz Sine, 2Vpp | 2Vpp Sine | Negligible | < 1° | Well within the 3MHz gain-bandwidth product. |
| 1MHz Sine, 2Vpp | Clipped/Distorted | N/A | > 45° lag | Slew rate limit (13V/µs) and GBW exceeded. |
| DC 16V (Exceeds +15V rail) | -13V (Slammed) | mA range | N/A | Phase inversion fault. Output flips to negative rail. |
Why a Voltage Follower Over an Emitter Follower?
Before op-amps were cheap, designers used a BJT common-collector (emitter follower) to buffer signals. You might also ask why not just use a direct wire. Here is the decision matrix for why the op-amp topology wins in precision analog design:
| Parameter | Op-Amp Voltage Follower | BJT Emitter Follower | Direct Wire |
|---|---|---|---|
| Input Impedance | > 10^12 Ω (JFET/CMOS) | ~10kΩ to 100kΩ | Equals Source Z |
| Output Impedance | < 1 Ω (closed-loop) | ~10 Ω to 50 Ω | Equals Source Z |
| Voltage Offset | < 5 mV (can be nV) | ~0.6V (V_be drop) | 0V |
| Drive Capability | 20mA - 40mA typical | High (depends on BJT) | Limited by Source |
Choose the op-amp follower when: You need to buffer a high-impedance sensor (like a piezo pickup or pH probe) without loading it down, and you require DC accuracy without the 0.6V base-emitter drop of a transistor.
Choose the BJT emitter follower when: You need to drive heavy currents (amps) that would melt a standard op-amp output stage, and you can tolerate the V_be voltage drop.
Design Walkthrough: Real Component Values
Let us design a buffer for an audio signal chain using the TL072. While the theoretical schematic shows just the IC and a direct feedback wire, a bench-ready design requires support components to prevent oscillation and noise.
In an ideal JFET op-amp, the feedback path is a direct 0Ω wire. However, if you use a bipolar input op-amp like the LM358, input bias current (typically 20nA) flowing through a high-impedance source creates a DC offset voltage. To cancel this, insert a feedback resistor (R_f) equal to the source impedance. For our TL072 audio buffer with a 10kΩ source pot, the 5pA bias current creates only 50µV of offset, so a direct wire is perfectly fine.
Bill of Materials & Values:
- U1: TL072 Dual JFET Op-Amp (DIP-8 package).
- C1, C2 (Decoupling): 100nF X7R MLCC capacitors. Place these within 2mm of pins 8 (V+) and 4 (V-) to ground. This shunts high-frequency switching noise.
- C3, C4 (Bulk Reserve): 10µF aluminum electrolytic capacitors on the power rails for low-frequency transient current.
- R_iso (Output Isolation): 47Ω series resistor on the output pin. Why? If your load has >100pF of parasitic capacitance (like a long coaxial cable), the capacitive load interacts with the op-amp's output impedance, degrading phase margin and causing high-frequency ringing. The 47Ω resistor isolates the feedback loop from the capacitive load.
Failure Modes: What Breaks at the Extremes?
Understanding how the circuit fails is critical for debugging. Here is what happens when elements break or exceed limits:
- Open Feedback Loop (Pin 2 floats): The negative feedback is severed. The op-amp reverts to open-loop comparator mode. The massive 200,000x gain amplifies microvolt input offset voltages, slamming the output instantly to either the positive or negative supply rail. Fix: Check for cold solder joints or broken jumper wires on the inverting node.
- Short to Ground on Non-Inverting Input (Pin 3): The output will faithfully follow the input down to 0V. On a dual-supply TL072, it will actually sink current and pull slightly below ground (down to about -1.5V saturation limit). On a single-supply LM358, it will pull to within 20mV of the negative rail.
- Exceeding Common-Mode Input Range: The TL072 datasheet specifies a common-mode voltage limit of ±11V on a ±15V supply. If you inject a 14V signal, the internal differential pair starves for bias current. This triggers phase inversion—the output violently snaps to the negative rail (-13V) instead of following the input. Fix: Use a rail-to-rail input op-amp like the OPA2134 if your signal approaches the supply rails.
Step-by-Step Breadboard Testing Procedure
Do not just plug in the IC and apply power. Follow this sequence to verify the op-amp configuration safely and accurately.
- Verify Power Rails First: Before inserting the TL072, power your breadboard. Use a digital multimeter (DMM) to verify pin row V+ is +15.0V (±0.1V) and V- is -15.0V. Ensure they are not reversed.
- Seat the IC and Decouple: Insert the TL072 spanning the center trench. Install the 100nF MLCCs directly from pin 8 to the ground rail, and pin 4 to the ground rail. Power down to insert the IC if you are prone to bending pins.
- Wire the Feedback: Use a short, stiff jumper wire to connect Pin 1 (Output A) directly to Pin 2 (Inverting Input A). Connect your signal source to Pin 3 (Non-Inverting Input A).
- Inject a DC Test Voltage: Use a bench power supply or a trimmed potentiometer to feed 2.5V DC into Pin 3. Measure the output at Pin 1 with your DMM. It should read 2.5V (±5mV).
- Test AC Response and Ringing: Switch to a function generator. Inject a 10kHz square wave, 2Vpp. Probe the output with an oscilloscope using a 10x probe (ensure the probe compensation cap is tuned). Look at the rising edges. If you see high-frequency ringing (oscillation), your load is too capacitive. Insert the 47Ω isolation resistor between Pin 1 and your probe point to dampen the resonance.
For deeper reading on buffer stability and impedance interactions, refer to the voltage follower chapter in All About Circuits. By selecting the right op-amp topology and respecting the physical limits of the silicon, your buffer will pass signals transparently without loading down your source.
