A voltage dependent voltage source (VDVS) is an active circuit element whose output voltage is mathematically proportional to a controlling voltage measured across two other nodes in the same circuit. You cannot buy a discrete "VDVS" component at an electronics distributor; instead, it is a foundational mathematical building block used in circuit theory and simulation to model the behavior of real active devices like operational amplifiers, transistors, and vacuum tubes.
The Core Concept: What a VDVS Actually Does
In circuit analysis, a VDVS (often called a Voltage-Controlled Voltage Source, or VCVS) is defined by the equation Vout = μ · Vx, where Vx is the controlling voltage and μ is a dimensionless voltage gain factor.
What it changes in a real circuit: In theoretical analysis and SPICE simulation, the VDVS changes how we solve complex feedback networks. An ideal VDVS provides infinite input impedance at the sensing nodes (drawing exactly zero current) while providing zero output impedance at the delivery nodes (capable of sourcing infinite current). This allows engineers to isolate high-impedance sensor signals from low-impedance power stages without loading effects, enabling precise impedance transformation and feedback loop stabilization.
The Water Analogy: Think of a VDVS like a municipal water pressure booster pump. The pump doesn't generate water out of nowhere; it senses the pressure in the main city line (the controlling voltage) and multiplies that pressure to push water up a high-rise building (the output voltage), all without restricting the flow or drawing water from the main city line itself.
Common Confusion: Beginners frequently confuse a VDVS with an independent voltage source (like a 12V battery or bench supply) or a voltage-dependent current source (VDCS). An independent source outputs a fixed value regardless of the rest of the circuit. A VDCS, on the other hand, outputs a current based on a sensed voltage (transconductance), which is how MOSFETs are typically modeled, whereas a VDVS outputs a voltage.
Worked Numeric Example: Modeling an Op-Amp Open Loop
Let us use real numbers to model a standard Texas Instruments LM741 op-amp in its open-loop configuration using a VDVS. According to the datasheet, the LM741 has a typical DC open-loop voltage gain (AOL) of 200,000 (roughly 106 dB).
- Non-inverting input (V+): Tied to a precision reference of 5.00005 V.
- Inverting input (V-): Tied to a feedback network sitting at 5.00000 V.
- Controlling voltage (Vx): V+ - V- = 5.00005 V - 5.00000 V = 0.00005 V (50 μV).
Using the VDVS equation, we calculate the output:
Vout = AOL × Vx = 200,000 × 0.00005 V = 10 V.
The ideal VDVS outputs exactly 10.0 V, assuming it is powered by ±15V rails and has not hit saturation.
But what happens if V+ drops to 4.99990 V? The differential voltage Vx becomes -0.00010 V. The math dictates Vout = -20 V. However, because the real LM741 is powered by ±15V rails, the physical output clips at roughly -13V (accounting for internal bipolar transistor saturation voltage drops). To model this accurately in SPICE, we cannot use a simple linear VDVS; we must use a non-linear VDVS with a TABLE or LIMIT function to enforce the ±13V saturation boundaries.
Where You Meet This in Practice
You will never solder a physical "VDVS" to a PCB, but you will encounter its mathematical equivalent constantly in engineering workflows:
- SPICE Netlists and Simulators: In LTspice, PSpice, or ngspice, the VDVS is instantiated using the
Eprefix. A basic netlist entry looks likeE1 out 0 in+ in- 100000, which tells the simulator to create a source named E1 between 'out' and ground, controlled by the voltage difference between 'in+' and 'in-', with a gain of 100,000. For complex behavioral modeling, engineers use the LTspice simulator to implement Laplace transforms directly inside the E-source to model frequency-dependent gain roll-off. - Op-Amp Macro-Models: When semiconductor manufacturers release SPICE models for op-amps (like the OPA140), they do not simulate every single internal transistor. Instead, they build a macro-model using a VDVS for the gain stage, combined with resistors and capacitors to simulate the dominant pole, output impedance, and common-mode rejection ratio (CMRR).
- Negative Impedance Converters (NICs): In advanced analog design, NICs are used to cancel out parasitic capacitance or resistance. The theoretical foundation of a NIC relies entirely on the VCVS behavior of the op-amp to force a node to exhibit a negative Thevenin resistance.
VDVS vs. Other Dependent Sources
Circuit theory relies on four types of dependent sources. Confusing them leads to fundamentally broken SPICE models and incorrect small-signal analysis. Here is how the VDVS stacks up against the rest, as taught in foundational MIT OpenCourseWare circuit electronics curricula:
| Source Type | Input Sensed | Output Generated | Gain Unit | Real-World Equivalent |
|---|---|---|---|---|
| VDVS (VCVS) | Voltage | Voltage | Dimensionless (V/V) | Op-amp, Ideal Transformer |
| VDCS (VCCS) | Voltage | Current | Transconductance (Siemens) | MOSFET, OTA (e.g., LM13700) |
| CDVS (CCVS) | Current | Voltage | Transimpedance (Ohms) | Photodiode TIA, Current Sense Amp |
| CDCS (CCCS) | Current | Current | Dimensionless (A/A) | BJT (Beta/hFE), Current Mirror |
Frequently Asked Questions
Can I buy a physical voltage dependent voltage source component?
No, a VDVS is a theoretical construct. However, you can buy operational amplifiers, which are the closest physical realization. An ideal op-amp is literally a VDVS with infinite open-loop gain, infinite input impedance, and zero output impedance. Real op-amps approximate this behavior within their power supply rails and bandwidth limits.
Why does my SPICE simulation fail to converge with a VDVS?
Convergence failures with E-sources usually happen for two reasons. First, you have a floating node: the controlling nodes (in+ and in-) lack a DC path to ground, leaving the simulator unable to establish an initial operating point. Second, you have created an unstable infinite feedback loop with no phase margin or delay, causing the mathematical solver to oscillate endlessly between time steps. Always ensure a high-value resistor (e.g., 1 GΩ) to ground on high-impedance sensing nodes.
What is the difference between a VDVS and an ideal transformer?
While both scale voltage, an ideal transformer also scales current inversely to conserve power (Pin = Pout). A VDVS does not conserve power in a theoretical simulation; it can output infinite power to a load because it draws exactly zero power from the controlling nodes. If you need to model power conservation and impedance reflection in SPICE, use a behavioral transformer model or coupled inductors (K statement) rather than a standalone VDVS.
How do I add output impedance to a VDVS in SPICE?
An ideal VDVS has zero output impedance, meaning it can drive a 0.1 Ω load with 100A of current without the voltage sagging. To model a real device (like an op-amp with a 75 Ω output impedance), simply place a standard resistor (e.g., R_out 75) in series with the positive output node of the VDVS before it connects to the rest of your circuit load.
