The seven fundamental logic gates—AND, OR, NOT, NAND, NOR, XOR, and XNOR—form the physical bedrock of every digital system, from simple 555-timer latch circuits to 64-bit microprocessors. While software engineers simulate these gates in code, hardware builders must map abstract binary truth tables to physical voltage thresholds, propagation delays, and specific silicon part numbers. Below is the definitive reference chart for truth tables for all logic gates, followed by the exact decision path to select the right integrated circuit (IC) for your workbench.
The Master Reference: Truth Tables for All Logic Gates
How to read this table: Columns A and B represent the binary inputs (where 0 = Low and 1 = High), and column Y represents the resulting binary output. For the NOT gate, only input A is evaluated. This chart follows the positive logic convention and standard graphic symbols defined in IEEE Std 91-1984 / ANSI Y32.14. Bookmark the row IDs below for quick jump lookups when debugging breadboard circuits.
| Gate Type | Boolean Expression | Input A | Input B | Output Y |
|---|---|---|---|---|
| AND | Y = A · B | 0 / 0 / 1 / 1 | 0 / 1 / 0 / 1 | 0 / 0 / 0 / 1 |
| OR | Y = A + B | 0 / 0 / 1 / 1 | 0 / 1 / 0 / 1 | 0 / 1 / 1 / 1 |
| NOT | Y = A' | 0 / 1 | N/A | 1 / 0 |
| NAND | Y = (A · B)' | 0 / 0 / 1 / 1 | 0 / 1 / 0 / 1 | 1 / 1 / 1 / 0 |
| NOR | Y = (A + B)' | 0 / 0 / 1 / 1 | 0 / 1 / 0 / 1 | 1 / 0 / 0 / 0 |
| XOR | Y = A ⊕ B | 0 / 0 / 1 / 1 | 0 / 1 / 0 / 1 | 0 / 1 / 1 / 0 |
| XNOR | Y = (A ⊕ B)' | 0 / 0 / 1 / 1 | 0 / 1 / 0 / 1 | 1 / 0 / 0 / 1 |
Translating Logic to Voltage: Which Column Applies to Your Circuit?
A truth table operates in the abstract realm of 0s and 1s. On your workbench, those binary states map to specific voltage ranges. The column that applies to your installation depends entirely on your logic family and supply voltage (VCC). If you feed a 3.3V signal from an ESP32 into a standard 74LS TTL chip expecting 5V logic, the gate will read the HIGH state as an undefined floating voltage, resulting in erratic outputs.
Below are the critical input voltage thresholds ($V_{IL}$ for guaranteed LOW, $V_{IH}$ for guaranteed HIGH) for the most common 5V and 3.3V logic families. Always check the manufacturer datasheet for your exact part.
| Logic Family | Target VCC | $V_{IL}$ (Max LOW) | $V_{IH}$ (Min HIGH) | Best Use Case |
|---|---|---|---|---|
| 74HC (High-Speed CMOS) | 5.0V | 1.35V | 3.15V | Pure 5V CMOS systems |
| 74HCT (TTL-Compatible CMOS) | 5.0V | 0.8V | 2.0V | Interfacing 5V Arduino with older TTL |
| 74LVC (Low-Voltage CMOS) | 3.3V | 0.8V | 2.0V | 3.3V ESP32 / Raspberry Pi GPIO |
Extending the Table: Multi-Input and Fan-Out Derating
The master table above assumes 2-input gates. How do derating rows and extensions modify these base values when you scale up?
1. Multi-Input Extensions: If you use a 3-input AND gate (e.g., SN74HC11), the truth table expands from $2^2 = 4$ rows to $2^3 = 8$ rows. The rule remains identical: Output Y is 1 only when A=1, B=1, and C=1. However, physically, adding inputs increases the internal parasitic capacitance. Expect the propagation delay ($t_{pd}$) to increase by roughly 1-2 nanoseconds per additional input stage compared to the 2-input equivalent.
2. Fan-Out Derating: A truth table assumes an ideal, unloaded output. In reality, every gate output has a current limit. A standard 74HC output can source or sink roughly 25mA. If you connect the output of one AND gate to the inputs of ten other gates, you must calculate the DC fan-out. Each 74HC input draws about 1µA, meaning one HC output can theoretically drive hundreds of HC inputs. But if you are driving 74LS TTL inputs (which draw ~0.4mA per LOW input), a single 74HC output can only safely drive about 10 LS inputs before the output voltage sags below the $V_{IL}$ threshold, violating the truth table.
Decision Tree: Picking the Exact IC Part Number
Stop guessing which chip to order. Use this decision path to terminate your search with a concrete, purchasable part number based on your system voltage and logic requirement. We will use the Quad 2-Input AND Gate as the baseline example.
| IF your system is... | AND you need... | THEN buy this exact Part Number | Package / Footprint |
|---|---|---|---|
| 5V (e.g., Arduino Uno, 555 Timers) | Standard CMOS, low power | SN74HC08N | 14-pin PDIP (Through-hole) |
| 5V, but interfacing with legacy 74LS TTL | TTL-compatible input thresholds | SN74HCT08N | 14-pin PDIP (Through-hole) |
| 3.3V (e.g., ESP32, Raspberry Pi Pico) | Native 3.3V logic, high speed | SN74LVC08APWR | 14-pin TSSOP (SMD) |
| Automotive / High Temp (up to 125°C) | AEC-Q100 qualification | SN74LVC08A-Q1 | 14-pin SOIC (SMD) |
Note: The 'N' suffix denotes through-hole DIP packages ideal for breadboarding, while 'PWR' denotes TSSOP surface-mount packages for custom PCB fabrication. Always verify pinouts against the specific datasheet before soldering.
What the Truth Table Cannot Tell You
A truth table is a static, steady-state document. It defines what the output should be once all voltages have settled. It completely fails to capture the dynamic, real-world behavior of silicon. When debugging a circuit that 'works on paper' but fails on the oscilloscope, remember these three missing variables:
- Propagation Delay ($t_{pd}$): When input A transitions from 0 to 1, output Y does not change instantly. A 74HC08 at 5V has a typical $t_{pd}$ of 10ns. In high-speed clock circuits, this delay causes phase shifts and timing skew.
- Glitches and Timing Hazards: If an XOR gate receives two inputs that are supposed to change simultaneously (e.g., A goes 1->0 and B goes 0->1), slight differences in internal transistor switching speeds can cause the output to momentarily spike to a 0 before settling at 1. The truth table shows a clean 1->1 transition; the oscilloscope shows a 3ns glitch.
- Metastability: If an input voltage hovers exactly between $V_{IL}$ and $V_{IH}$ (the forbidden zone), the gate's internal feedback loops can oscillate or lock into an intermediate voltage state, drawing excessive current and potentially overheating the IC. Never leave logic inputs floating; always use 10kΩ pull-up or pull-down resistors to force a definitive truth table state.
