A truth table defines the exact boolean output for every possible input combination of a logic gate, but translating those abstract 1s and 0s into physical hardware requires mapping them to specific integrated circuit (IC) families. The default assumption for a standard 2-input AND gate is that a HIGH (1) output requires both inputs to be HIGH, but on a workbench, a 'HIGH' means anything above the specific minimum input voltage threshold ($V_{IH}$) of your chosen logic family. Below is the master reference chart for truth table logic gates, followed by the voltage threshold columns, timing blind spots, and a concrete decision tree to select the exact part number for your next build.
The Master Truth Table Logic Gates Reference
This table covers the seven fundamental logic gates. The symbols conform to ANSI/IEEE Std 91-1984, which is the standard for graphic symbols for logic functions. How to read this table: Columns A and B represent the binary inputs (0 = LOW/GND, 1 = HIGH/VCC). Column Y is the resulting output. The 'Common 5V IC' column provides the standard 74-series Quad package part number, assuming a 5V VCC supply and standard through-hole DIP packaging.
| Gate Type | A | B | Output (Y) | ANSI/IEEE Symbol Shape | Boolean Expression | Common 5V IC (Quad) |
|---|---|---|---|---|---|---|
| AND | 0/0/1/1 | 0/1/0/1 | 0/0/0/1 | D-shaped (flat back, curved front) | Y = A · B | 74HC08 |
| OR | 0/0/1/1 | 0/1/0/1 | 0/1/1/1 | Curved back, pointed front | Y = A + B | 74HC32 |
| NOT | 0/1 | N/A | 1/0 | Triangle with output bubble | Y = A' | 74HC04 (Hex) |
| NAND | 0/0/1/1 | 0/1/0/1 | 1/1/1/0 | AND shape with output bubble | Y = (A · B)' | 74HC00 |
| NOR | 0/0/1/1 | 0/1/0/1 | 1/0/0/0 | OR shape with output bubble | Y = (A + B)' | 74HC02 |
| XOR | 0/0/1/1 | 0/1/0/1 | 0/1/1/0 | OR shape with double curved back | Y = A ⊕ B | 74HC86 |
| XNOR | 0/0/1/1 | 0/1/0/1 | 1/0/0/1 | XOR shape with output bubble | Y = (A ⊕ B)' | 74HC266 |
Real-World Voltage Thresholds: Which Column Applies?
The binary 1s and 0s in the table above are idealizations. In physical silicon, logic levels are defined by voltage thresholds. When designing a circuit, you must consult the $V_{IH}$ (Minimum HIGH input voltage) and $V_{IL}$ (Maximum LOW input voltage) columns of your specific IC's datasheet. These thresholds 'derate' the ideal truth table by introducing a forbidden zone (the noise margin) where the output becomes unpredictable.
For example, if you are interfacing a 3.3V ESP32 microcontroller with a 5V logic gate, which column applies? If you choose a standard 74HC family gate powered at 5V, its $V_{IH}$ is typically $0.7 \times V_{CC}$ (3.5V). The ESP32's 3.3V HIGH output falls into the forbidden zone, and the gate may read it as a LOW, breaking your truth table. You must instead select a 74HCT (TTL-compatible) or 74LVC family, which recognizes 2.0V as a valid HIGH even when powered at 5V.
What the Truth Table Cannot Tell You
A boolean truth table assumes instantaneous switching and infinite drive capability. Physical ICs violate both assumptions. When debugging a circuit that 'should' work according to the table but fails at high speeds, you are hitting these three physical limitations:
- Propagation Delay ($t_{pd}$): The output does not change the exact nanosecond the input changes. A standard 74HC08 at 5V has a typical $t_{pd}$ of 14ns. If you cascade four AND gates, the final output will be delayed by ~56ns. In high-speed SPI or ADC clocking, this delay causes setup/hold time violations.
- Fan-Out Limits: The truth table assumes an output can drive infinite inputs. In reality, a 74HC output can typically source/sink only 25mA. If you wire one AND gate output to ten LED indicators without buffer transistors, the voltage will sag below the $V_{OH}$ (Minimum HIGH output voltage) threshold, causing downstream gates to misread the state.
- Metastability: If inputs A and B of an XOR gate change state at the exact same picosecond, the output may enter a metastable state—hovering between HIGH and LOW—before resolving. Truth tables do not account for race conditions.
Decision Path: Picking the Right Logic Family IC
Use this decision tree to terminate your component search with a concrete, purchasable part number. This framework accounts for supply voltage, logic level compatibility, and packaging needs.
| If Your System Requires... | Then Choose This Logic Family | Concrete Part Number (AND Gate Example) | Why This Pick Wins |
|---|---|---|---|
| Standard 5V breadboard prototyping with 5V Arduinos | 74HC (High-speed CMOS) | 74HC08 (DIP-14) | Wide 2V-6V operating range, high noise immunity, standard pinout. |
| Interfacing 3.3V MCU outputs to a 5V powered gate | 74HCT (TTL-compatible CMOS) | 74HCT08 (DIP-14) | Accepts 2.0V as a valid HIGH while powered at 5V, solving the ESP32/RPi level-shift problem. |
| Native 3.3V systems, low power, tight PCB space | 74LVC (Low-Voltage CMOS) | 74LVC1G08 (SOT-23-5) | Single-gate package, operates down to 1.65V, ultra-fast 4ns propagation delay. |
| 12V automotive or industrial relay driving | CD4000B Series | CD4081 (DIP-14) | Operates from 3V to 15V. Can interface directly with 12V control signals without regulators. |
Quick-Jump Bookmark Rows for Common Debugging Scenarios
When your physical circuit defies the standard digital logic theory, use this quick-jump reference to diagnose the failure mode.
- Symptom: Output is stuck HIGH regardless of inputs. Fix: Check for a short to VCC on the output pin, or verify that the IC is not a 74LS family suffering from a missing pull-up resistor on an open-collector output (e.g., 74LS03).
- Symptom: XOR gate acts like an OR gate. Fix: One of your inputs is likely floating or experiencing severe ground bounce. Measure the voltage at the input pin relative to the IC's GND pin (Pin 7), not the breadboard's ground rail.
- Symptom: Gate outputs are inverted from the truth table. Fix: You are likely using a NAND (74HC00) or NOR (74HC02) IC by mistake, or your oscilloscope probe is set to AC coupling, masking the DC offset and inverting the visual trigger.
- Symptom: Intermittent flipping of states when a motor turns on. Fix: Your noise margin is compromised. Add a 0.1µF ceramic decoupling capacitor directly across VCC (Pin 14) and GND (Pin 7) of the logic IC to suppress inductive voltage spikes.
For comprehensive electrical characteristics and timing diagrams across all modern logic families, refer to the Texas Instruments Logic Circuit Overview and cross-reference your specific part number's datasheet before finalizing your PCB layout.
