A pure mathematics truth table definition describes a matrix showing all possible Boolean input combinations and their resulting outputs. But on the electronics workbench, a truth table is a physical voltage map. It defines the exact input threshold voltages required to force an output stage into a valid logic state. When you are debugging a mixed-signal board or interfacing an ESP32 with legacy 5V logic, the abstract 1s and 0s are useless. You need the physical voltage thresholds, noise margins, and fan-out limits that dictate whether your circuit will actually work.
This reference guide translates the theoretical truth table into a physical hardware lookup chart, using the industry-standard 74HC (High-Speed CMOS) and CD4000 logic families as our baseline.
The Master Logic Gate Truth Table (IEEE/ANSI Reference)
The table below bridges the gap between Boolean algebra and physical silicon. It maps the ideal logic states to the actual voltage thresholds defined in the Texas Instruments SN74HC series datasheets and IEEE Std 100-2000.
| Gate Type | Input A | Input B | Ideal Output | V_IH (Min) for '1' | V_IL (Max) for '0' |
|---|---|---|---|---|---|
| AND (74HC08) | 0 | 0 | 0 | 3.5V | 1.0V |
| 0 | 1 | 0 | |||
| 1 | 0 | 0 | |||
| 1 | 1 | 1 | |||
| OR (74HC32) | 0 | 0 | 0 | 3.5V | 1.0V |
| 0 | 1 | 1 | |||
| 1 | 0 | 1 | |||
| 1 | 1 | 1 | |||
| NAND (74HC00) | 0 | 0 | 1 | 3.5V | 1.0V |
| 0 | 1 | 1 | |||
| 1 | 0 | 1 | |||
| 1 | 1 | 0 | |||
| XOR (74HC86) | 0 | 0 | 0 | 3.5V | 1.0V |
| 0 | 1 | 1 | |||
| 1 | 0 | 1 | |||
| 1 | 1 | 0 |
Translating Ideal States to Physical Hardware
When wiring up a circuit, you must determine which column applies to your installation. If you are driving a 5V 74HC gate from a 3.3V microcontroller (like an ESP32 or Raspberry Pi Pico), you must look at the V_IH (Min) column. As shown above, a 74HC gate requires a minimum of 3.5V to register a logic HIGH. A 3.3V GPIO pin will fail to trigger the gate, resulting in a floating or LOW state. To fix this, you must either use a logic level shifter or switch to 74HCT series ICs, which feature TTL-compatible input thresholds (V_IH = 2.0V).
How Loading Modifies the Base Truth Table
In wire sizing, thermal derating reduces ampacity. In logic gates, fan-out loading modifies the base truth table output. The ideal output column assumes zero current draw. However, if you connect multiple gate inputs to a single output, or drive an LED directly from a logic pin, you draw current.
- Sinking Current (Output LOW): If you exceed the gate's maximum I_OL (e.g., sinking >4mA on a standard CD4011B), the output voltage (V_OL) rises from a crisp 0.1V to a murky 1.5V. The next stage in your circuit may misread this '0' as a '1'.
- Sourcing Current (Output HIGH): Similarly, drawing too much current pulls the V_OH down below the V_IH threshold of the receiving gate.
Always check the DC output current limits in the datasheet. The truth table guarantees the logic state only if the load remains within the specified fan-out limits (typically 10 LS-TTL loads or 50 pF capacitive load for standard CMOS).
What the Truth Table Cannot Tell You
A common mistake among hobbyists is assuming the truth table represents instantaneous, guaranteed behavior. The truth table is a static DC model. It completely hides three critical dynamic hardware realities:
The truth table does not show a row for "Disconnected" or "Floating" inputs. In CMOS logic (74HC, CD4000), a floating input acts as an antenna, picking up electromagnetic noise. This causes the internal MOSFETs to rapidly switch on and off simultaneously, creating a direct short from VCC to GND. The IC will overheat and fail. Always tie unused CMOS inputs to VCC or GND via a 10kΩ resistor.
- Propagation Delay (t_pd): When inputs change, the output does not flip instantly. A standard 74HC08 has a propagation delay of roughly 15ns at 5V. In high-speed clock circuits, this delay causes phase shifts and timing violations that the truth table ignores.
- Setup and Hold Times: For sequential logic (flip-flops, latches like the 74HC573), the data input must be stable for a specific number of nanoseconds before and after the clock edge. Violating these times leads to metastability, where the output oscillates or settles at an intermediate voltage.
- Power-On Reset States: The truth table assumes the IC is fully powered and stable. During the VCC ramp-up phase, outputs can glitch or latch into high-current states before the internal bias networks stabilize.
Quick-Jump Debugging Reference for Common Logic ICs
Bookmark this section for rapid bench debugging. These are the most queried physical ICs and their specific edge cases, as detailed in standard digital logic references.
| IC Part Number | Function | Pin 14 / Pin 7 | Common Debugging Failure Mode |
|---|---|---|---|
| 74HC08 | Quad 2-Input AND | VCC / GND | Output stuck LOW. Usually caused by one input floating LOW or VCC dropping below 4.5V under load. |
| 74HC32 | Quad 2-Input OR | VCC / GND | Output stuck HIGH. Check for a short to VCC on the PCB trace or a failed pull-up resistor on an input. |
| 74HC04 | Hex Inverter (NOT) | VCC / GND | Oscillation on output. Caused by leaving an unused inverter section floating. Tie unused inputs to GND. |
| 74HC86 | Quad 2-Input XOR | VCC / GND | Phase detector errors. Often caused by exceeding the max propagation delay skew between the two input paths. |
| CD4011B | Quad 2-Input NAND (4000 Series) | VDD / VSS | Sluggish switching. 4000-series is slow; t_pd can exceed 100ns at 5V. Do not use for >1MHz clocks. |
Understanding the truth table definition as a physical voltage and timing specification—not just a math exercise—is what separates theoretical circuit design from reliable hardware engineering. Always verify your logic levels with an oscilloscope or logic analyzer, and never trust a '1' or '0' until you have measured the actual voltage at the pin.
