A transmission gate is a bidirectional, voltage-controlled electronic switch built from parallel NMOS and PMOS transistors that passes both analog and digital signals with minimal rail-to-rail voltage drop. In a real circuit, it changes how we route signals by eliminating the threshold voltage ($V_{th}$) loss inherent in single-MOSFET pass transistors, allowing signals to swing fully from GND to $V_{CC}$ without degradation. Beginners commonly confuse the transmission gate with tri-state buffers (which are unidirectional digital drivers that cannot pass arbitrary analog voltages) or standard logic gates (which compute Boolean functions rather than passing raw continuous voltages).
Inside the Transmission Gate Schematic: How Parallel MOSFETs Solve the Threshold Problem
To understand why the transmission gate schematic is necessary, you first have to look at the failure mode of a single MOSFET pass transistor. If you use a single NMOS transistor as a switch to pass a 5V logic HIGH, the output will only reach $5V - V_{th}$ (roughly 4.3V for a typical logic-level NMOS). The transistor stops conducting once the source voltage rises to the gate voltage minus the threshold drop. Conversely, a single PMOS transistor passes a strong 5V HIGH but fails to pull the signal all the way down to 0V, stopping at $V_{th}$ above ground.
The transmission gate solves this by wiring an NMOS and a PMOS transistor in parallel. Their source and drain terminals are tied together, creating a bidirectional path. The gates are driven by complementary control signals: the NMOS gate receives the control signal ($C$), while the PMOS gate receives the inverted control signal ($\bar{C}$).
Think of it like a paired two-lane toll bridge. A single NMOS is like a bridge that always charges a $1 toll (the threshold drop) to high-clearance vehicles (high voltages). The transmission gate adds a second PMOS lane that waives the toll for high-clearance vehicles but charges it for low-clearance vehicles (low voltages). Because the two lanes operate in parallel, every vehicle gets through for free, resulting in a full 0V to 5V swing with no threshold penalty.
When $C$ is HIGH (e.g., 5V), the NMOS turns on strongly to pass low voltages (near GND), while the PMOS turns on strongly to pass high voltages (near $V_{CC}$). In the middle of the voltage range, both transistors share the current. This parallel topology results in a relatively flat, low on-resistance ($R_{ON}$) across the entire operating range, which is critical for analog signal integrity.
Worked Numeric Example: Sizing and Delay in a 74HC4066 Analog Switch
Let us look at real numbers using one of the most common transmission gate ICs on the bench: the Texas Instruments 74HC4066 quad bilateral switch. This IC contains four independent transmission gates.
Assume we are operating the 74HC4066 at $V_{CC} = 5V$. According to the datasheet, the typical on-resistance ($R_{ON}$) is 80 Ω when passing signals near the middle of the rail. Let us calculate the signal degradation and propagation delay in two different real-world loading scenarios.
Scenario A: Driving a High-Impedance Microcontroller ADC
You are routing a 5V analog sensor signal through the transmission gate into an Arduino ADC pin, which presents an input impedance of roughly $10\text{ k}\Omega$ (ignoring the brief sampling capacitor charging phase).
- Voltage Drop: Using the voltage divider formula, $V_{out} = 5V \times (10,000 / (10,000 + 80)) = 4.96V$.
- Attenuation: The signal loses only $40\text{ mV}$, an error of 0.8%. For a 10-bit ADC (4.88mV per step), this is an 8-step offset, easily calibrated out in software.
Scenario B: Driving a 50 Ω Oscilloscope Termination
You are using the 74HC4066 to switch a high-speed digital pulse into a 50 Ω terminated oscilloscope input to measure edge rates.
- Voltage Drop: $V_{out} = 5V \times (50 / (50 + 80)) = 1.92V$.
- Attenuation: You lose 61.6% of your signal amplitude. The 5V pulse now looks like a 1.92V pulse, which might fail to trigger a 3.3V logic analyzer.
Calculating RC Propagation Delay
Transmission gates introduce an RC low-pass filter effect due to their $R_{ON}$ and the parasitic capacitance of the PCB trace and load. If your PCB trace and load present a combined capacitance ($C_L$) of $20\text{ pF}$:
$\tau = R_{ON} \times C_L = 80\ \Omega \times 20\text{ pF} = 1.6\text{ ns}$.
For a digital signal to settle to 99% of its final value, it takes roughly $4.6\tau$, meaning your edge will be smeared by about 7.36 ns. This is perfectly fine for I2C (100 kHz to 1 MHz) but will severely round the edges of a 50 MHz SPI clock.
Where You Meet This in Practice: Real-World ICs and Routing
You rarely build a transmission gate from discrete MOSFETs on a breadboard. The schematic requires the PMOS and NMOS bodies to be tied to their respective rails to prevent forward-biasing the parasitic body diodes, which is difficult without specialized isolated-well CMOS processes. Instead, you buy them integrated into specific functional blocks.
| Application / IC Type | Common Part Numbers | Why Transmission Gates are Used |
|---|---|---|
| Analog Multiplexers | CD4051, 74HC4051, ADG708 | Allows routing one of several analog sensor inputs to a single ADC without degrading the DC voltage level. |
| I2C Bus Switches | PCA9548A, TCA9548A | I2C is a bidirectional protocol. Standard logic buffers only drive one way. Transmission gates pass the bidirectional SDA line transparently without breaking the protocol. |
| Sample-and-Hold Circuits | LF398 (internal topology) | Passes an analog voltage to a hold capacitor, then isolates it. The bidirectional nature ensures the cap charges to the exact input potential. |
| FPGA Routing Matrices | Xilinx/Altera internal fabric | Millions of microscopic transmission gates are used to route logic signals between LUTs and flip-flops inside the silicon die. |
Transmission Gate Schematic FAQs
Why does a transmission gate schematic require both an NMOS and a PMOS transistor?
A single NMOS transistor suffers from a threshold voltage drop when passing a HIGH signal, meaning a 5V input might only yield a 4.2V output. A single PMOS suffers from a similar drop when passing a LOW signal. By placing them in parallel, the NMOS handles the low-voltage portion of the signal swing efficiently, while the PMOS handles the high-voltage portion, ensuring the output can reach both the exact GND and exact $V_{CC}$ rails without degradation.
Can I use a transmission gate IC to switch high-voltage AC mains power?
No. Standard CMOS transmission gate ICs like the 4066 or 4051 series are strictly limited to their $V_{CC}$ and GND rails (typically 3V to 15V maximum). Applying 120V or 230V AC mains will instantly destroy the silicon junction and create a severe shock and fire hazard. For switching AC mains, you must use electromechanical relays, solid-state relays (SSRs) with back-to-back SCRs or TRIACs, or properly rated high-voltage MOSFETs with isolated gate drivers.
How does a transmission gate differ from a tri-state buffer in digital logic?
A tri-state buffer (like the 74HC125) is an active digital driver that sources or sinks current to forcefully drive a logic HIGH or LOW, and enters a high-impedance state when disabled. It is unidirectional and only understands discrete logic levels. A transmission gate is a passive, bidirectional resistive switch. It does not amplify or drive the signal; it merely connects two nodes together. You use tri-state buffers for digital bus contention management, and transmission gates for routing raw analog voltages or bidirectional digital buses like I2C.
What happens to the control signal inverters in a discrete transmission gate design?
In a schematic, the PMOS gate requires the logical inverse of the NMOS gate control signal. In integrated circuits, this is handled by a tiny, internal CMOS inverter powered by the same rails. If you attempt to build a transmission gate from discrete MOSFETs (like a 2N7000 and an IRF9540), you must provide your own external logic inverter (like a 74HC04) to generate the complementary gate drive. Furthermore, discrete designs often fail at passing the full rail-to-rail voltage because standard discrete MOSFETs have parasitic body diodes that will conduct if the signal swings outside the bounds of the discrete source/drain biasing.
