The Standard Boolean Logic Table (Truth Tables)
A boolean logic table (commonly called a truth table) maps every possible combination of binary inputs to a single binary output. While software engineers treat these tables as abstract math, hardware builders must treat them as physical voltage targets. Before wiring up a 74-series or 4000-series IC, you must understand both the mathematical truth and the electrical reality.
| Input A | Input B | AND | OR | NAND | NOR | XOR | XNOR |
|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 |
| 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 |
| 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 |
| 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 |
For a deeper breakdown of gate-level schematics and IEC 60617 symbol standards, refer to the All About Circuits Digital Textbook. However, knowing that a NAND gate outputs a '1' when both inputs are '0' is only half the battle. You must know what voltage constitutes a '1' in your specific installation.
Translating Math to Silicon: Logic Family Voltage Thresholds
The boolean table assumes perfect 0s and 1s. In physical reality, logic gates operate on analog voltage thresholds defined by standards like JEDEC JESD8C. The table below bridges the gap between abstract boolean math and physical bench measurements.
Which column applies to your installation? If you are interfacing a 5V Arduino Uno with a 74HC00 chip, use the 5V CMOS (74HC) row. If you are wiring a 3.3V ESP32-WROOM-32 to a level shifter or modern logic IC, use the 3.3V CMOS (LVC) row. Never mix 5V TTL outputs directly into 1.8V or 3.3V inputs without a voltage divider or level translator; you will destroy the silicon.
| Logic Family (Standard) | VCC (Nominal) | V_IL (Max Low Input) | V_IH (Min High Input) | V_OL (Max Low Output) | V_OH (Min High Output) | DC Noise Margin |
|---|---|---|---|---|---|---|
| 5V TTL (74LS) | 5.0V | 0.8V | 2.0V | 0.4V | 2.7V | 0.4V / 0.7V |
| 5V CMOS (74HC) | 5.0V | 1.5V | 3.5V | 0.1V | 4.9V | 1.4V / 1.4V |
| 3.3V CMOS (LVC) | 3.3V | 0.8V | 2.0V | 0.4V | 2.4V | 0.4V / 1.2V |
| 1.8V CMOS | 1.8V | 0.45V | 1.17V | 0.2V | 1.4V | 0.25V / 0.23V |
Source: Thresholds derived from JEDEC JESD8C specifications and Texas Instruments Logic Portfolio datasheets for standard 74-series families.
How Derating and Fan-Out Modify Base Values
The values in the table above assume ideal conditions: a single load, 25°C ambient temperature, and zero parasitic trace inductance. In practice, fan-out loading and temperature derating shrink your noise margins.
- Fan-Out Derating: Every logic input draws a small amount of leakage current. If you connect one 74HC00 NAND output to ten different inputs (exceeding the typical fan-out of 4-6 for high-speed CMOS), the output transistors cannot source enough current to maintain the $V_{OH}$ minimum. Your 4.9V high output might sag to 3.8V under load, pushing it dangerously close to the $V_{IH}$ threshold and causing intermittent logic errors.
- Temperature Derating: As CMOS junction temperatures approach 85°C or 125°C (common in enclosed industrial panels), the threshold voltages shift. The $V_{IH}$ minimum typically drops, but the $V_{OH}$ capability also degrades. Always derate your maximum allowable fan-out by 20% to 30% if your enclosure lacks active cooling.
What the Boolean Table Cannot Tell You
A boolean logic table is a static, zero-time snapshot. It is entirely blind to the temporal physics of semiconductor switching. When debugging a circuit that 'should' work according to the truth table but fails on the oscilloscope, you are likely facing one of these three physical limitations:
- Propagation Delay ($t_{pd}$): A 74HC00 gate takes roughly 8 to 15 nanoseconds for a change at input 'A' to reflect at output 'Y'. In high-speed clock circuits, cascading multiple gates creates cumulative delay, leading to race conditions where signals arrive at a flip-flop out of phase.
- Metastability: If an input voltage lingers in the undefined region between $V_{IL}$ and $V_{IH}$ (e.g., a slow-rising RC circuit or a bouncing mechanical switch), the gate's internal transistors can enter a linear state. The output may oscillate at high frequencies or lock at an intermediate voltage (e.g., 2.5V), violating the boolean table entirely.
- Ground Bounce: When multiple outputs on a single IC (like a 74HC595 shift register) switch from High to Low simultaneously, the sudden surge of current through the ground pin's parasitic inductance causes the chip's internal ground reference to spike. This can falsely register as a logic '1' on adjacent inputs.
Frequently Asked Questions
How do I read a boolean logic table for a 3-input gate?
A 3-input gate (like a 74HC10 triple 3-input NAND) requires a truth table with $2^3 = 8$ rows. The inputs are typically labeled A, B, and C. The binary counting sequence for the inputs runs from 000 to 111. For a 3-input NAND gate, the output is '1' for every row except the final row (111), where the output is '0'. When wiring this on a breadboard, ensure you account for the extra input pin by tying it High if you only need a 2-input function, otherwise the gate will remain locked.
Which logic family column applies to my 3.3V microcontroller installation?
If you are using an ESP32, STM32, or Raspberry Pi Pico operating at 3.3V, you must look at the 3.3V CMOS (LVC) row. The 74LVC family (e.g., SN74LVC1G08) is specifically designed with 5V-tolerant inputs, meaning you can safely feed it 5V signals while it is powered by 3.3V, making it the ultimate bridge chip for mixed-voltage workbenches. Do not use standard 74HC chips powered at 5V to read 3.3V ESP32 outputs, as the 3.3V High signal falls below the 74HC $V_{IH}$ minimum of 3.5V.
How do temperature and fan-out derating modify base logic values?
Derating shrinks your DC Noise Margin. If a 5V CMOS gate has a baseline $V_{OH}$ of 4.9V and a $V_{IH}$ of 3.5V, your noise margin is a healthy 1.4V. If you exceed the fan-out limit by driving 15 inputs, the $V_{OH}$ might sag to 3.8V. If the ambient temperature rises and shifts the receiving gate's $V_{IH}$ up to 3.7V, your noise margin collapses to 0.1V. At this point, minor EMI from a nearby switching relay will easily flip the logic state, causing phantom triggers.
Why does my physical circuit output differ from the boolean truth table?
If your multimeter reads an output that contradicts the boolean table, check for three physical faults: First, measure the VCC pin directly at the IC body (not at the power supply) to ensure you don't have voltage drop across thin breadboard rails. Second, check for 'floating' inputs; unconnected CMOS pins will drift and cause unpredictable outputs. Third, verify your ground connections. A missing ground pin on a 14-pin DIP IC will cause the chip to attempt to ground itself through the input protection diodes of connected signal lines, resulting in bizarre, non-boolean logic states.
