Designing a Transistor as Amplifier Circuit: Common Emitter Bias & Values

The Default Pick: Common Emitter Topology and Node Labels

When you need voltage gain from a single discrete bipolar junction transistor (BJT), the Common Emitter (CE) with voltage-divider bias is the undisputed default. It provides high voltage gain, moderate input impedance, and a predictable output phase inversion. While Common Collector (emitter follower) is better for current buffering, and Common Base is reserved for high-frequency RF stages, the CE topology is what you reach for to amplify an audio or sensor signal from millivolts to volts.

To design this, we must first lock in our node labels. Every calculation and measurement in this guide references these exact points:

• $V_{CC}$: The positive DC supply rail (we will use 12V).
• GND: The 0V reference plane.
• $V_{in}$: The AC signal input, coupled through capacitor $C_{in}$.
• $V_{out}$: The amplified AC signal, extracted via capacitor $C_{out}$.
• Base (B): The control node where the bias network and AC signal meet.
• Collector (C): The output node where the load resistor ($R_C$) drops voltage.
• Emitter (E): The stabilizing node tied to GND through the emitter resistor ($R_E$).

Design Walkthrough: Sizing Real Components for a 2N3904

Let’s build a general-purpose small-signal amplifier. We are using a 2N3904 NPN transistor, a $V_{CC}$ of 12V, and targeting a quiescent collector current ($I_C$) of 1mA. This current provides a good balance between low noise and sufficient drive capability.

Step 1: Set the Emitter Resistor ($R_E$)

For thermal stability, the DC voltage drop across the emitter resistor ($V_E$) should be roughly 10% of $V_{CC}$.

• Target $V_E = 1.2V$.
• Since $I_E \approx I_C = 1mA$, we calculate $R_E = V_E / I_E = 1.2V / 1mA = 1.2k\Omega$.
• Concrete Pick: Use a standard E12 1.2kΩ resistor.

Step 2: Set the Collector Resistor ($R_C$)

To maximize symmetrical AC voltage swing without clipping, the DC voltage at the collector ($V_C$) should sit roughly halfway between $V_{CC}$ and $V_E$.

• Target $V_C = 6.5V$.
• The voltage drop across $R_C$ must be $V_{CC} - V_C = 12V - 6.5V = 5.5V$.
• $R_C = 5.5V / 1mA = 5.5k\Omega$.
• Concrete Pick: Use a standard E12 5.6kΩ resistor. (This shifts $V_C$ slightly to 6.4V, which is perfectly acceptable).

Step 3: Design the Base Voltage Divider ($R_1$ and $R_2$)

The base voltage ($V_B$) must be exactly one diode drop ($V_{BE} \approx 0.7V$) higher than $V_E$.

• $V_B = V_E + 0.7V = 1.2V + 0.7V = 1.9V$.
• To make the divider "stiff" (immune to base current loading), the current flowing through $R_1$ and $R_2$ should be at least 10 times the maximum expected base current ($I_B$).
• Assuming a worst-case minimum $\beta$ of 100, $I_B = I_C / \beta = 1mA / 100 = 10\mu A$.
• Target divider current $I_{div} = 10 \times 10\mu A = 100\mu A$.
• $R_2 = V_B / I_{div} = 1.9V / 100\mu A = 19k\Omega$. Concrete Pick: 18kΩ (standard E12).
• $R_1 = (V_{CC} - V_B) / I_{div} = (12V - 1.9V) / 100\mu A = 101k\Omega$. Concrete Pick: 100kΩ (standard E12).

Step 4: Coupling Capacitors ($C_{in}$ and $C_{out}$)

To pass audio frequencies down to 20Hz without attenuating the signal, we need capacitors that present a low reactance relative to the circuit impedance. The input impedance of this stage is roughly $R_1 || R_2 || (\beta \times R_E) \approx 13k\Omega$. A 1µF ceramic or film capacitor yields a high-pass cutoff of roughly 12Hz. Use 1µF for both $C_{in}$ and $C_{out}$.

Behavior Matrix: How Component Changes Shift the Bias Point

When you are tuning this circuit on the bench, you need to know exactly what happens when you swap a resistor. Here is the behavioral matrix for the CE topology designed above.

Failure Mode Contrast: What Breaks at the Extremes?

A robust design requires knowing how the circuit fails when a component goes open or short. This is critical for troubleshooting a dead breadboard.

$R_1$ (Upper Divider Resistor) Opens

Symptom: $V_{out}$ is stuck at 12V DC; no AC signal passes.
Mechanism: With $R_1$ open, the base is pulled to GND entirely through $R_2$. $V_B = 0V$. The B-E junction is not forward-biased. The transistor enters hard cutoff. $I_C = 0A$, meaning there is zero voltage drop across $R_C$, leaving $V_C$ at $V_{CC}$ (12V).

$R_2$ (Lower Divider Resistor) Shorts to GND

Symptom: Identical to $R_1$ opening. $V_{out}$ stuck at 12V DC.
Mechanism: A shorted $R_2$ forces $V_B$ directly to 0V. The transistor cuts off. Note: If $R_2$ shorts to $V_{CC}$ instead of GND, $V_B$ jumps to 12V, forcing massive base current, driving the transistor into deep saturation ($V_C \approx 0.2V$), and likely exceeding the B-E junction's maximum current rating.

$R_E$ (Emitter Resistor) Opens

Symptom: $V_C$ sits at 12V; $V_B$ reads roughly 1.9V; $V_E$ reads 0V.
Mechanism: An open emitter breaks the primary current path. No emitter current can flow, which means no collector current can flow. The transistor is effectively removed from the circuit, despite the base having the correct bias voltage.

$R_C$ (Collector Resistor) Shorts

Symptom: $V_C$ reads exactly 12V. AC output is zero.
Mechanism: The collector is tied directly to the supply rail. While the transistor is still biased and conducting internally, the AC voltage signal has no load resistor across which to develop a varying voltage drop. The AC signal is shorted to the AC-ground of the power supply.

Breadboard Verification: Step-by-Step Testing Protocol

Do not just plug in the signal generator and hope for the best. Follow this strict sequence to verify the DC bias before applying AC.

1. Build the DC Bias Network Only: Insert the 2N3904, $R_1$, $R_2$, $R_C$, and $R_E$. Wire $V_{CC}$ to 12V and GND. Do not install $C_{in}$ or $C_{out}$ yet.
2. Verify Quiescent Voltages: Power the supply. Use a digital multimeter (DMM) to measure DC voltages relative to GND.
   • $V_B$ should read $\approx 1.9V$ ($\pm 0.2V$).
   • $V_E$ should read $\approx 1.2V$ ($\pm 0.2V$).
   • $V_C$ should read $\approx 6.4V$ ($\pm 1.0V$).
   If these are correct, your Q-point is stable. If $V_C$ is near 12V or near 0V, check for reversed transistor pins (the 2N3904 pinout is E-B-C, flat side facing you).
3. Add AC Coupling: Power down. Insert the 1µF $C_{in}$ and $C_{out}$ capacitors. Ensure the polarity is correct if using electrolytics (positive side toward the higher DC voltage node).
4. Inject the Test Signal: Set your function generator to a 1kHz sine wave. Crucial: Set the amplitude to 50mV peak-to-peak (mVpp). Because our unbypassed gain is ~4.6, a 50mVpp input will yield a ~230mVpp output, keeping us well within the linear region.
5. Measure the Output: Connect an oscilloscope to the output side of $C_{out}$. Set the scope to AC coupling. You should see a clean, 230mVpp sine wave that is exactly 180° out of phase with the input signal. If the wave is flattened at the top or bottom, your input amplitude is too high, or your DC bias drifted.

Topology Decision Tree: When to Pivot Away from Common Emitter

The Common Emitter is the workhorse, but it is not a universal solution. Use this decision matrix to select the correct single-transistor topology for your specific constraint.