A 4th order Butterworth filter is an electronic circuit that passes a specific range of frequencies while attenuating others at a steep rate of -24 dB per octave, maintaining a perfectly flat amplitude response without ripple in the passband. If you are sampling analog sensors with a microcontroller or cleaning up audio DAC outputs, this specific filter topology is often the exact tool you need to eliminate out-of-band noise without distorting the signals you care about.

What it changes in a real circuit: Compared to a standard 2nd-order filter (-12 dB/octave roll-off), a 4th order Butterworth doubles the attenuation slope to -80 dB/decade. This drastically shrinks the "transition band" between your passband and stopband, killing high-frequency aliasing before it hits your ADC or smoothing PWM carrier frequencies into a pure DC/analog voltage.

The Core Definition and Common Confusions

The defining characteristic of any Butterworth filter is its "maximally flat" passband. Unlike Chebyshev filters, which achieve a steeper roll-off by allowing amplitude ripple in the passband, or Bessel filters, which sacrifice roll-off steepness to preserve phase linearity (time-domain step response), the Butterworth prioritizes a perfectly flat magnitude response up to the cutoff frequency ($f_c$).

The most common mistake makers and junior engineers make with a 4th order Butterworth filter is naive cascading. A 4th order filter is built by cascading two 2nd-order stages. However, you cannot simply cascade two identical 2nd-order Butterworth stages (each with a Q-factor of 0.707). If you do, the resulting 4th-order filter will exhibit a +3 dB resonant peak right at the cutoff frequency, ruining the flat passband. To achieve a true 4th order Butterworth response, the Q-factors of the two stages must be staggered: Stage 1 must have a Q of 0.541, and Stage 2 must have a Q of 1.307.

Worked Numeric Example: 1 kHz Active Low-Pass Design

Let's design a 4th order low-pass Butterworth filter with a cutoff frequency ($f_c$) of exactly 1,000 Hz. We will use the Sallen-Key unity-gain topology because it is stable, requires only one op-amp per stage, and is highly forgiving of op-amp gain-bandwidth limitations.

To achieve the required staggered Q-factors (0.541 and 1.307) while keeping resistor values identical for easy sourcing, we manipulate the capacitor ratios. We will use standard E96 series 1% resistors and C0G/NP0 5% capacitors.

Target: $f_c$ = 1,000 Hz | Topology: Cascaded Sallen-Key Unity Gain | Op-Amp: Dual channel (e.g., TL072 or OPA2277)
Stage Target Q-Factor R1 (1%) R2 (1%) C1 (C0G) C2 (C0G)
Stage 1 0.541 15.8 kΩ 15.8 kΩ 18 nF 5.6 nF
Stage 2 1.307 15.8 kΩ 15.8 kΩ 27 nF 3.9 nF

The Math Check: The cutoff frequency for a Sallen-Key stage is $f_c = 1 / (2\pi \sqrt{R_1 R_2 C_1 C_2})$. For Stage 1, plugging in 15.8kΩ and the 18nF/5.6nF capacitor pair yields approximately 1,003 Hz. Stage 2 yields roughly 981 Hz. In analog design, this minor stagger is absorbed by the overall 4th-order polynomial response, resulting in a combined -3 dB point precisely at 1,000 Hz.

Pro-Tip: Always wire Stage 1 (the lower Q, broader stage) before Stage 2 (the higher Q, sharper stage). If you reverse them, the high-Q Stage 2 will clip or distort on large transient signals before the signal ever reaches Stage 1, severely degrading your total harmonic distortion (THD) performance.

Where You Meet This in Practice

You will rarely see a 4th order Butterworth filter used for basic audio tone controls, but it is the undisputed king in three specific applications:

  • Anti-Aliasing for High-Resolution ADCs: If you are feeding a 16-bit ADC (like the ADS1115) or using the internal SAR ADC on an ESP32 to sample a 50 Hz load cell, you must filter out 50/60 Hz mains hum and high-frequency switching noise. A 4th order Butterworth set to 100 Hz provides -80 dB of attenuation at 1 kHz, ensuring no high-frequency noise folds back into your digital sampling band.
  • PWM to Analog Conversion: When using an Arduino or ESP32 to generate a pseudo-analog voltage via PWM (e.g., at 20 kHz), a simple 1st-order RC filter leaves noticeable ripple. A 4th order Butterworth tuned to 2 kHz will completely obliterate the 20 kHz carrier wave, leaving a pristine DC voltage with microvolt-level ripple.
  • Vibration and Shock Analysis: In piezoelectric sensor conditioning, you often need to isolate low-frequency mechanical resonance from high-frequency acoustic noise. The steep -24 dB/octave skirt of the Butterworth allows you to pass the mechanical signal while aggressively rejecting the acoustic noise floor.

Decision Tree: Which Filter Order and Type to Pick

Choosing the wrong filter wastes board space or ruins your signal integrity. Use this decision matrix to lock in your topology.

If your primary constraint is... And your signal type is... Then choose this filter:
Eliminating ADC aliasing / Nyquist folding Slow-moving DC or low-freq AC (sensors) 4th Order Butterworth (Flat passband, steep stopband)
Preserving square-wave edges / step response Digital pulses, PWM, video signals 4th Order Bessel (Linear phase, no ringing)
Maximum rejection in a narrow transition band RF or audio where minor passband ripple is acceptable 4th Order Chebyshev Type I (Steepest roll-off, 1dB ripple)
Minimal component count / low power budget Battery-powered, non-critical LED dimming 2nd Order Passive RC (No op-amps required)

The Default Pick: If you are designing an anti-aliasing front-end for a microcontroller ADC and are unsure which to pick, default to a 4th Order Butterworth using an OPA2277 dual op-amp. It provides the best balance of flat amplitude response, aggressive noise rejection, and low DC offset error.

Implementation Gotchas: Op-Amps and Tolerances

Theoretical schematics often fail on the bench because of two physical realities: Gain-Bandwidth Product (GBW) and capacitor dielectrics.

The GBW Rule of Thumb

An op-amp's open-loop gain drops as frequency increases. For an active filter to behave according to its mathematical model, the op-amp's GBW must be significantly higher than the filter's cutoff frequency, scaled by the Q-factor of the highest-Q stage. The rule of thumb is:

$GBW > 100 \times f_c \times Q_{max}$

In our 1 kHz example, $Q_{max}$ is 1.307. Therefore, $GBW > 100 \times 1000 \times 1.307 = 130.7$ kHz. A classic TL072 (3 MHz GBW) works perfectly here. However, if you shift this same design to a 100 kHz cutoff for an SDR (Software Defined Radio) front-end, you suddenly need an op-amp with >13 MHz GBW, like the TI OPA2134 or the LMH6629. Using a low-GBW op-amp at high frequencies will cause the filter to peak violently and oscillate.

The Capacitor Dielectric Trap

Never use X7R or Y5V ceramic capacitors in the feedback loop of a high-Q active filter. These Class II dielectrics exhibit severe voltage coefficients (capacitance drops as voltage increases) and microphonics (they act as piezoelectric microphones, converting board vibration into electrical noise). Always specify C0G (NP0) dielectrics for filter capacitors. If C0G values above 10 nF are too expensive or physically large, switch to film capacitors (like WIMA FKP or Panasonic PPS) for the larger values.

Frequently Asked Questions

Can I just use a digital FIR/IIR filter in my ESP32 instead of an analog 4th order Butterworth?
No. Digital filters can only process signals that have already been sampled. If high-frequency noise (above the Nyquist limit) enters your ADC, it aliases into the digital domain as low-frequency noise. A digital filter cannot remove aliasing after the fact; you must use an analog anti-aliasing filter before the ADC pin.

Why not just use a 6th or 8th order Butterworth for even steeper roll-off?
Every additional 2nd-order stage adds another op-amp, more thermal noise, more DC offset error, and more board space. A 4th order (-24 dB/octave) is the "sweet spot" for 90% of embedded systems. If you need steeper rejection than a 4th order provides, you usually need to increase your ADC sampling rate and rely on a digital decimation filter downstream.

Do I need to match the impedances between Stage 1 and Stage 2?
In a Sallen-Key unity-gain configuration, the output impedance of Stage 1 is effectively zero (driven by the op-amp's output), so it will not load down Stage 2. You do not need to scale the resistor values between stages, which allows you to use identical resistor values across the whole board to reduce your BOM line count.

For further reading on active filter topologies and pole-zero placement, refer to the Analog Devices Active Filter Tutorial and the comprehensive All About Circuits filter design guide.