When you pull up a table of logic gates, you are usually looking for one of two things: the Boolean truth table that defines the gate's logical operation, or the electrical specification table that tells you how the physical silicon will behave on your breadboard. Most textbook references only provide the former, leaving makers to guess why their 3.3V ESP32 fails to trigger a 5V 74HC chip. This reference provides both, grounded in real bench measurements and JEDEC/TI datasheet standards.
Master Logic Family Specification Reference
Before wiring any IC, you must select the correct logic family. The table below maps the most common through-hole and SMD logic families used in DIY and prototyping. Source Standard: Thresholds and delays are derived from standard JEDEC JESD8C CMOS specifications and manufacturer datasheets (Texas Instruments SN74 series, NXP HEF4000B series) at an ambient temperature ($T_A$) of 25°C.
| Logic Family | Typical Part Example | $V_{CC}$ Range | $V_{IH}$ (Min HIGH) | $V_{IL}$ (Max LOW) | $t_{pd}$ (Typ Delay) | Max Fan-Out |
|---|---|---|---|---|---|---|
| 74LS (TTL) | 74LS00 (NAND) | 4.75V - 5.25V | 2.0V | 0.8V | 9 ns | 10 LS loads |
| 74HC (CMOS) | 74HC04 (Inverter) | 2.0V - 6.0V | 3.15V (at 4.5V $V_{CC}$) | 1.35V (at 4.5V $V_{CC}$) | 14 ns | 10 LSTTL or high $C_L$ |
| 74HCT (TTL-compat CMOS) | 74HCT245 (Transceiver) | 4.5V - 5.5V | 2.0V | 0.8V | 18 ns | 15 LSTTL loads |
| 4000B (Standard CMOS) | CD4011 (NAND) | 3.0V - 15.0V | 3.5V (at 5V $V_{CC}$) | 1.5V (at 5V $V_{CC}$) | 50 ns | 1 (Low current drive) |
How to Read This Table
The $V_{CC}$ Range column dictates your power supply rails; operating outside this will cause erratic behavior or silicon damage. The $V_{IH}$ (Voltage Input HIGH) and $V_{IL}$ (Voltage Input LOW) columns are the most critical for microcontroller interfacing. They define the minimum voltage the chip guarantees to read as a logical '1' and the maximum it guarantees to read as a '0'. The $t_{pd}$ (Propagation Delay) is the time it takes for a change at the input to reflect at the output, measured at 25°C with a standard 15pF capacitive load.
If you are designing the power supply, look at the $V_{CC}$ column. If you are interfacing a microcontroller (like an Arduino Uno or ESP32) to the gate's inputs, the $V_{IH}$ and $V_{IL}$ columns are your primary constraint. For example, an ESP32 outputs 3.3V for a HIGH signal. If you feed that into a 74HC chip running at 5V, the 74HC requires a minimum of 3.15V to register a HIGH. While 3.3V technically passes, noise margins are razor-thin. The correct engineering choice is to use the 74HCT family, which requires only 2.0V for a HIGH, guaranteeing rock-solid 3.3V compatibility.
Standard Logic Gate Truth Tables (Quick-Jump)
These are the fundamental Boolean logic tables. Bookmark this section for quick reference when debugging state machines or writing firmware bit-masks. For all tables below, 0 = LOW and 1 = HIGH.
| Gate Type | Boolean Expression | Input A | Input B | Output Y |
|---|---|---|---|---|
| AND | Y = A · B | 0 / 0 / 1 / 1 | 0 / 1 / 0 / 1 | 0 / 0 / 0 / 1 |
| OR | Y = A + B | 0 / 0 / 1 / 1 | 0 / 1 / 0 / 1 | 0 / 1 / 1 / 1 |
| NAND | Y = NOT (A · B) | 0 / 0 / 1 / 1 | 0 / 1 / 0 / 1 | 1 / 1 / 1 / 0 |
| NOR | Y = NOT (A + B) | 0 / 0 / 1 / 1 | 0 / 1 / 0 / 1 | 1 / 0 / 0 / 0 |
| XOR | Y = A ⊕ B | 0 / 0 / 1 / 1 | 0 / 1 / 0 / 1 | 0 / 1 / 1 / 0 |
| XNOR | Y = NOT (A ⊕ B) | 0 / 0 / 1 / 1 | 0 / 1 / 0 / 1 | 1 / 0 / 0 / 1 |
| NOT (Inverter) | Y = NOT A | 0 / 1 | N/A | 1 / 0 |
Note: The NAND gate is considered 'universal' because any other logic gate can be constructed using only NAND gates. This is heavily utilized in FPGA fabric and ASIC design to minimize transistor count variations.
Derating, Fan-Out, and What the Table Cannot Tell You
Datasheet tables provide baseline numbers under ideal laboratory conditions. On a real workbench, parasitic elements and loading alter these values significantly.
How Derating Modifies Base Values
Propagation delay ($t_{pd}$) and maximum operating frequency are not static; they derate based on capacitive load ($C_L$) and supply voltage ($V_{CC}$).
- Capacitive Derating: A 74HC04 datasheet lists a typical $t_{pd}$ of 14ns at $V_{CC}$ = 5V and $C_L$ = 15pF. If you route a long PCB trace or wire the output to 10 other gate inputs (raising $C_L$ to roughly 50pF), the delay derates linearly. Expect the actual propagation delay to stretch to 45ns–50ns. This phase shift can cause timing violations in high-speed shift registers like the 74HC595.
- Voltage Derating: CMOS gates slow down as voltage drops. Running a 4000B series chip at 3.3V instead of 5V will roughly double its propagation delay. Always check the $V_{CC}$ vs. $t_{pd}$ graph in the manufacturer's datasheet if your project runs off a draining Li-Ion cell.
Fan-Out Limitations
Fan-out defines how many inputs a single output can reliably drive. While modern CMOS inputs draw virtually zero DC current (allowing a theoretical DC fan-out of thousands), AC fan-out is limited by capacitance. Every CMOS input adds about 3pF to 5pF of capacitance. If your driver gate can only tolerate 50pF before its rise/fall times degrade enough to cause excessive heat or logic errors, your practical AC fan-out is limited to about 10 to 15 gates. For higher loads, use a dedicated buffer like the 74HCT244.
What the Table Cannot Tell You
No reference table accounts for physical layout anomalies. Specifically, tables will not warn you about:
- Metastability: If an input signal transitions exactly as the clock edge arrives at a flip-flop, the output may hover between HIGH and LOW, or oscillate, before settling. Truth tables assume instantaneous, perfectly synchronized transitions.
- Ground Bounce and Ringing: When multiple outputs in a 74-series IC switch from HIGH to LOW simultaneously, the sudden surge of current through the ground pin's inductance can cause the internal ground reference to spike. This 'ground bounce' can momentarily push a LOW input above the $V_{IL}$ threshold, causing a false HIGH reading.
- Floating Inputs: CMOS tables assume inputs are driven to a valid logic level. A floating (unconnected) CMOS input acts as an antenna, picking up EMI and causing the internal transistors to oscillate in the linear region, leading to rapid overheating and IC destruction. Always tie unused inputs to $V_{CC}$ or GND via a 10kΩ resistor.
For deeper dives into specific timing diagrams and absolute maximum ratings, always consult the original manufacturer datasheets via Texas Instruments Logic or NXP Logic Families, and review foundational digital theory at All About Circuits.
