When drafting schematics or writing hardware description language (HDL), the symbols of truth table logic dictate how your circuit is interpreted by both humans and EDA software. There is no single universal standard; instead, you must choose between the ANSI/IEEE Std 91 distinct-shape symbols (dominant in US academia, hobbyist, and commercial PCB design) and the IEC 60617-12 rectangular symbols (standard in European industrial PLC and military schematics). Selecting the wrong standard for your target environment causes library mismatches in KiCad or Altium and confusion during board bring-up.
The Quick-Reference Logic Symbol & Truth Table Chart
The following spec-sheet-table maps the fundamental logic gates across both major standards. Bookmark this section for quick-jump lookups when wiring 7400-series ICs or drafting custom logic blocks.
| Gate Name | ANSI/IEEE Symbol Shape | IEC 60617 Symbol Notation | Boolean Equation | Base Truth Table (A, B → Y) |
|---|---|---|---|---|
| AND | D-shaped (flat left, curved right) | Rectangle with & inside | Y = A · B | 0,0→0 | 0,1→0 | 1,0→0 | 1,1→1 |
| OR | Curved left, pointed right | Rectangle with ≥1 inside | Y = A + B | 0,0→0 | 0,1→1 | 1,0→1 | 1,1→1 |
| NOT (Inverter) | Triangle with output bubble | Rectangle with 1 inside, output bubble | Y = A' | 0→1 | 1→0 |
| NAND | D-shape with output bubble | Rectangle with & inside, output bubble | Y = (A · B)' | 0,0→1 | 0,1→1 | 1,0→1 | 1,1→0 |
| NOR | Curved/pointed with output bubble | Rectangle with ≥1 inside, output bubble | Y = (A + B)' | 0,0→1 | 0,1→0 | 1,0→0 | 1,1→0 |
| XOR | OR shape with extra curved input line | Rectangle with =1 inside | Y = A ⊕ B | 0,0→0 | 0,1→1 | 1,0→1 | 1,1→0 |
| XNOR | XOR shape with output bubble | Rectangle with =1 inside, output bubble | Y = (A ⊕ B)' | 0,0→1 | 0,1→0 | 1,0→0 | 1,1→1 |
How to Read the Chart: Columns, Environments, and State Derating
To use this chart effectively, you must understand which column applies to your specific installation environment and how real-world physics "derates" the ideal 1s and 0s shown in the base truth table.
Which Column Applies to Your Installation?
- ANSI/IEEE Column: Applies to PCB schematic capture (KiCad, Altium, Eagle), academic textbooks, and breadboard wiring diagrams. EDA tools default to these distinct shapes because they are visually distinct at a glance, reducing routing errors.
- IEC 60617 Column: Applies to industrial control panels, PLC ladder/FBD logic, and European military/aerospace schematics. The rectangular format scales better for complex, multi-input custom arrays (like PALs/GALs) where drawing a distinct shape for a 12-input AND gate is impractical.
- Boolean Column: Applies directly to Verilog/VHDL coding and Arduino C++ logic statements.
How Logic Families "Derate" the Base Truth Table
A truth table shows ideal binary states (0 and 1). In physical silicon, these states are represented by voltage thresholds, and just like wire ampacity derates with heat, logic noise margins derate with temperature and VCC variations.
For example, look at the AND gate truth table. A "1" input means different things depending on the IC family:
- 74LS (TTL): A logic "1" requires a minimum of 2.0V. A logic "0" is anything below 0.8V. The noise margin is relatively tight.
- 74HC (CMOS): A logic "1" requires 0.7 × VCC (3.5V at a 5V supply). A logic "0" is anything below 0.3 × VCC (1.5V).
If you run a 74HC08 AND gate at 3.3V instead of 5V, the threshold for a "1" derates to 2.31V. If your microcontroller outputs 2.8V, it registers as a 1. But if ambient temperature rises to 85°C, leakage currents shift the threshold, potentially shrinking your noise margin and causing the physical gate to output a "0" when the truth table dictates a "1". Always check the datasheet's Recommended Operating Conditions table to see how voltage and temperature derate your logic thresholds.
Decision Tree: Which Symbol Standard Should You Use?
Do not mix symbol standards in a single schematic. Use this decision-tree-table to lock in your concrete pick before opening your EDA software.
| If Your Project Is... | Then Choose... | Concrete Pick / Action |
|---|---|---|
| A commercial PCB, hobbyist build, or Arduino/ESP32 shield designed in KiCad or Altium. | ANSI/IEEE Std 91 (Distinct Shapes) | Select the 74xx_IEEE or Logic_IEEE symbol library in your EDA tool. |
| An industrial PLC program, HMI screen, or European control panel schematic. | IEC 60617 (Rectangular) | Use the IEC 61131-3 standard FBD blocks in your PLC IDE (e.g., TIA Portal, RSLogix). |
| A complex programmable logic device (CPLD/FPGA) with gates exceeding 4 inputs. | IEC 60617 (Rectangular) | Use rectangular symbols; distinct shapes become visually cluttered past 4 inputs. |
| Writing firmware (C/C++) or HDL (Verilog/VHDL). | Boolean Operators | Use && (AND), || (OR), ! (NOT) in C; &, |, ~ in Verilog. |
What the Table Cannot Tell You: Propagation Delay and Fan-Out
The symbols of truth table logic represent ideal, instantaneous Boolean math. They completely hide the physical limitations of the silicon. If you are designing a high-speed clock circuit or driving heavy loads, the truth table will lead you astray if you ignore these two factors:
1. Propagation Delay ($t_{pd}$)
When input A transitions from 0 to 1, output Y does not change instantly. The truth table implies it does, but physical gates have a propagation delay. For a standard SN74HC00N (NAND) operating at 5V, the typical $t_{pd}$ is 14 ns. If you cascade four of these gates in series to build a deeper logic tree, you accumulate 56 ns of delay. In a 20 MHz system (50 ns clock period), that cascaded delay will cause a setup-time violation and crash your state machine. The symbol won't warn you; only the datasheet's switching characteristics table will.
2. Fan-Out and Let-Through Current
A truth table shows one output driving one input. In reality, you must calculate fan-out. A standard 74LS TTL output can sink 8 mA (Low state) and source 0.4 mA (High state). Because a 74LS input draws about 0.4 mA when Low, the maximum fan-out is 8 mA / 0.4 mA = 20 LS inputs. If you wire 25 inputs to a single 74LS08 AND gate output, the voltage in the Low state will derate, rising above the 0.8V threshold and being falsely read as a logic "1" by downstream gates. CMOS families (like 74HC) have virtually infinite DC fan-out due to high-impedance inputs, but their AC fan-out is limited by capacitive loading, which increases propagation delay.
Handling 'X' and 'Z': The Hidden Truth Table States
Basic truth tables only show 0 and 1. Advanced digital design requires two additional states that modify how you read and draft logic:
- X (Don't Care): Used in Karnaugh maps and HDL case statements. It tells the synthesizer, "I don't care if this output is 0 or 1 for this specific input combination." The compiler will choose whichever state results in fewer logic gates, optimizing your FPGA fabric or reducing transistor count in an ASIC.
- Z (High-Impedance): Represents a disconnected state, crucial for tri-state buffers (like the 74HC125). When the enable pin is inactive, the output goes to 'Z', effectively removing it from the circuit so another device can drive the shared I2C or SPI bus. If you forget to add pull-up/pull-down resistors to a 'Z' state line, the floating pin will act as an antenna, picking up EMI and causing erratic logic switching.
For a deeper dive into how logic families interact with these thresholds, refer to the All About Circuits Digital Textbook on Logic Gates, or consult the Texas Instruments Logic Family Overview for exact $t_{pd}$ and fan-out specifications for modern 74HC, 74LVC, and 74AUC series ICs.
