The standard IEEE/ANSI symbol for a NOR gate is a curved OR-gate shield with a small inversion bubble at the output tip, while the IEC 60617 standard uses a rectangular block marked with an internal '≥1' and an output bubble. A NOR gate outputs a HIGH (1) only when all inputs are LOW (0). Below is the complete reference chart for logic symbols, regional standard variants, and critical IC pinout data.
NOR Gate Symbol and Logic Reference Chart
Depending on your region and the era of the schematic you are reading, the symbol for a NOR gate will change. The table below maps the primary drafting standards to their visual representations, Boolean expressions, and truth tables.
| Standard / Region | Visual Shape Description | Boolean Expression | Truth Table (A, B → Y) |
|---|---|---|---|
| IEEE/ANSI Std 91 (US / Global Modern) |
Curved 'D' shield (OR shape) with a small circle (bubble) on the output tip. | Y = (A + B)' | 0,0 → 1 0,1 → 0 1,0 → 0 1,1 → 0 |
| IEC 60617-12 (EU / International) |
Rectangular block. Inside contains the qualifier '≥1' (or 'OR'), with a bubble on the output line. | Y = (A + B)' | 0,0 → 1 0,1 → 0 1,0 → 0 1,1 → 0 |
| DIN 40700 (Legacy German / Obsolete) |
Rectangular block with a '1' inside and an overline spanning the inputs, or a small triangle/bubble on output. | Y = A NOR B | 0,0 → 1 0,1 → 0 1,0 → 0 1,1 → 0 |
| MIL-STD-806 (US Military / Aerospace) |
Identical to IEEE/ANSI curved shield, but strictly enforces aspect ratios and bubble diameter relative to line weight. | Y = (A + B)' | 0,0 → 1 0,1 → 0 1,0 → 0 1,1 → 0 |
What Each Row Means in Practice
- IEEE/ANSI (Curved Shield): This is what you will see on 95% of modern datasheets from manufacturers like Texas Instruments, NXP, and Microchip. The curved back distinguishes it from the straight-backed AND/NAND gates.
- IEC (Rectangular): Standard in European industrial automation, PLC ladder logic printouts, and IEC-compliant electrical schematics. The '≥1' means 'one or more inputs must be high to trigger the base OR function', and the bubble inverts it.
- DIN (Legacy): You will only encounter this when repairing or retrofitting old European industrial control panels (pre-1990s). Treat it identically to the IEC standard, but be aware that the overline notation implies active-low logic.
Standard NOR IC Pinouts and Electrical Characteristics
When moving from schematic symbols to the workbench, you need exact part numbers and pinouts. The most common physical implementation of the NOR gate is the Quad 2-Input NOR IC in a 14-pin DIP package. However, the pinout for the 7402 (NOR) is fundamentally different from the 7400 (NAND).
| Part Number | Logic Family | VCC Range | Typical Prop Delay (tpd) | Max Output Current (I_O) | Input Structure |
|---|---|---|---|---|---|
| SN74HC02 | High-Speed CMOS (HC) | 2.0V to 6.0V | 14 ns @ 5V | ±25 mA | MOSFET (High Z) |
| CD4001B | Standard CMOS (4000B) | 3.0V to 18.0V | 120 ns @ 5V | ±6.8 mA | MOSFET (High Z) |
| SN74LS02 | Low-Power Schottky (LS) | 4.75V to 5.25V | 10 ns @ 5V | +8 mA / -400 μA | Bipolar (TTL) |
| HEF4001B | High-Speed CMOS (HEF) | 3.0V to 15.0V | 100 ns @ 5V | ±2.5 mA | MOSFET (High Z) |
In a standard 7400 (NAND) IC, pins 1 and 2 are inputs, and pin 3 is the output. The 7402 (NOR) flips this arrangement. On a 7402, Pin 1 is the Output, while Pins 2 and 3 are the Inputs. If you wire a 7402 using the standard 7400 mental model, you will tie the output directly to your input signal bus. If that output is driving HIGH while your input switch pulls LOW, you will create a dead short through the silicon, instantly overheating and destroying the IC. Always verify pin 1 on a 7402 with a datasheet before applying power.
Silicon Reality: Why NOR is Slower and Larger than NAND
Looking at the propagation delays above, you might notice CMOS NOR gates (like the CD4001B) tend to be slightly slower and physically larger on silicon than their NAND equivalents. In a standard CMOS process, a 2-input NOR gate requires two PMOS transistors in series for the pull-up network, and two NMOS transistors in parallel for the pull-down network. Because holes (the charge carriers in PMOS) have lower mobility than electrons (in NMOS), putting PMOS transistors in series increases resistance. To compensate and maintain symmetrical rise/fall times, silicon foundries must make the PMOS transistors in a NOR gate physically wider. This takes up more die area and adds parasitic capacitance, which is why NAND gates are the universal default in flash memory and standard-cell ASIC design.
Misread Symbols, Faded Markings, and Standard Variants
When troubleshooting legacy hardware or reading poorly copied schematics, symbol misinterpretation is a primary cause of diagnostic errors. Here is how to handle the edge cases and rows people consistently get wrong.
Rows and Symbols People Get Wrong
- Confusing NOR with NAND: The inversion bubble is present on both. The differentiator is the back edge of the IEEE symbol. A NAND gate has a straight vertical back edge (AND shape). A NOR gate has a continuously curved back edge (OR shape). If the photocopy is blurred, look at the input lines: they connect to a curve on a NOR, but intersect a flat line on a NAND.
- The 'Exclusive' Trap: Do not confuse a standard NOR with an XNOR. An XNOR (Exclusive-NOR) will have an additional curved line detached from the input side of the shield, or a '2k' / '=' qualifier inside the IEC rectangle. A standard NOR gate has no secondary input curve.
- Active-Low Input Bubbles: In IEC and advanced IEEE schematics, you may see bubbles on the inputs of a gate alongside an OR shape. By De Morgan's Laws, an OR gate with inverted inputs is logically identical to a NAND gate. If you see an OR shape with input bubbles and no output bubble, it is functioning as a NAND, not a NOR.
Safe Interpretation of Faded or Missing IC Markings
If you are reverse-engineering a salvaged PCB and encounter an unmarked, faded, or custom-logged 14-pin DIP that you suspect is a quad NOR gate, do not guess based on circuit position alone. Use your multimeter to verify the internal protection diode network.
- Identify Power Rails: Assume Pin 14 is VCC and Pin 7 is GND (standard for 14-pin logic). Verify with a continuity test to the board's ground plane and decoupling capacitors.
- Set Multimeter to Diode Test: Place the red probe on GND (Pin 7) and the black probe on the suspected I/O pins.
- Read the Junction Drops: Standard TTL and CMOS logic gates have protection diodes on the inputs to prevent negative voltage spikes. However, the output pins feature a distinct pull-up/pull-down transistor network. On a standard CD4001B or 74HC02, the forward voltage drop measured from GND to an input pin will typically read as an open circuit (OL) or a very high diode drop (>2.0V) in this specific probe orientation, whereas the output pin will often show a distinct clamping diode drop (typically 1.2V to 1.5V) due to the output stage's VCC/GND protection network.
- Verify Logic: Power the board. Use a logic probe or oscilloscope. If Pin 1 goes HIGH only when both Pin 2 and Pin 3 are LOW, you have confirmed a NOR gate, regardless of what the faded silkscreen claims.
Always defer to the manufacturer's specific datasheet for exact timing diagrams and absolute maximum ratings. While the IEEE and IEC symbols provide a universal language for logic design, the physical silicon behavior—especially regarding propagation delay, fan-out limits, and pinout anomalies—dictates whether your circuit will function on the bench.
