Supercapacitors—technically known as Electrochemical Double-Layer Capacitors (EDLCs)—bridge the gap between traditional dielectric capacitors and electrochemical batteries. They offer capacitance measured in Farads rather than microfarads, but are restricted to low nominal voltages (typically 2.5V to 2.7V per cell). If you need to ride through a power dip for 5 seconds, buffer a 50A regenerative braking spike, or keep a real-time clock (RTC) alive for weeks, a supercapacitor is the correct component. However, picking the wrong form factor or ignoring equivalent series resistance (ESR) will result in catastrophic voltage sag or vented electrolyte.
Supercapacitor Topologies and Form Factors
Unlike ceramic capacitors, supercapacitors are categorized by their physical construction and internal chemistry rather than just their dielectric material. Selecting the right type depends entirely on your current draw, space constraints, and required cycle life. The table below maps the four primary commercial topologies to their real-world specifications.
| Type / Form Factor | Construction / Chemistry | Typical Cap & Tolerance | Temp Range / Cap Shift (Tempco) | ESR Range | Typical Use Case |
|---|---|---|---|---|---|
| Coin Cell (e.g., Panasonic EEC-EN0F204) |
Symmetric Carbon / Aqueous or Organic | 0.1F - 1.5F (-20% / +80%) |
-20°C to +70°C (-10% shift at -20°C) |
10Ω - 50Ω | RTC backup, memory retention, low-current bridge |
| Cylindrical (e.g., Eaton/Vishay 2.7V 100F) |
Symmetric Carbon / Organic Solvent | 10F - 3400F (-20% / +20%) |
-40°C to +65°C (-20% shift at -40°C) |
0.3mΩ - 30mΩ | Motor start, regen braking, high-current UPS |
| Pouch / Prismatic (e.g., Skeleton SKR) |
Asymmetric Carbon / Advanced Electrolyte | 50F - 500F (-10% / +30%) |
-40°C to +85°C (Stable to +65°C) |
1mΩ - 10mΩ | High-power pulse, grid stabilization, wind pitch control |
| Hybrid LIC (e.g., JM Energy LMC) |
Li-ion Battery + Carbon (Asymmetric) | 500F - 2300F (-10% / +20%) |
-30°C to +70°C (-15% shift at -30°C) |
1mΩ - 5mΩ | Energy recovery, extended ride-through, smart meters |
Which type for which job? Use coin cells strictly for microampere memory backup where space is at a premium. Use cylindrical EDLCs when you need massive, instantaneous current pulses (like welding or engine cranking) and can tolerate a 1-million-cycle lifespan. Choose Hybrid Lithium-Ion Capacitors (LICs) when you need higher energy density (longer hold-up times) and a higher cell voltage (3.8V), but be prepared to accept a lower cycle life (typically 50,000 to 100,000 cycles) compared to pure EDLCs.
Decoding Physical Markings and Datasheet Specs
Unlike small ceramic capacitors that rely on cryptic 3-digit EIA codes, commercial supercapacitors print their primary specifications directly on the shrink-wrap, aluminum can, or pouch. However, misinterpreting these markings can lead to immediate destruction of the part.
- Capacitance & Tolerance: Printed as
100F ±20%. Tolerance on EDLCs is notoriously wide. A -20% to +50% tolerance band is common for coin cells. Always design your hold-up circuit assuming the minimum guaranteed capacitance (the -20% figure). - Rated Voltage ($V_R$): E.g.,
2.7V. This is the absolute maximum continuous DC voltage. Exceeding this by even 0.1V accelerates electrolyte decomposition, generating internal gas and permanently increasing ESR. - Date/Lot Codes: Usually a 4-digit or alphanumeric string (e.g.,
2341for week 41 of 2023). Supercapacitors have a shelf life; if you are buying surplus stock older than 3 years, expect higher initial leakage currents until they undergo a reforming charge cycle. - Polarity Indicators: The negative terminal is heavily marked with a stripe, minus signs, or a distinct colored band. Reversing polarity on a charged supercapacitor causes rapid electrochemical breakdown and violent venting.
Safe Substitution and Sizing Framework
When the exact supercapacitor part number is out of stock, you can substitute safely, but you must follow strict electrical boundaries. According to application guidelines from manufacturers like Eaton, voltage ratings are non-negotiable downwards: you can substitute a 2.7V cell for a 2.5V cell, but never a 2.5V cell into a 2.7V circuit.
How to substitute safely:
Rule 1: Match or exceed the voltage rating.
Rule 2: Match or exceed the capacitance, factoring in the ESR voltage drop.
Rule 3: Ensure the physical footprint can handle the ripple current without exceeding the maximum core temperature (usually 65°C for standard organic electrolytes).
The Sizing Formula:
To calculate the required capacitance for a specific hold-up time, use the constant current discharge formula:
C = (I × t) / (V_initial - V_final)
Worked Example: You need to hold up a 3.3V microcontroller drawing 50mA for 10 seconds after a power loss. The MCU browns out at 2.5V. Assuming a direct discharge from 3.0V down to 2.5V:
C = (0.05A × 10s) / (3.0V - 2.5V) = 0.5 / 0.5 = 1.0F
However, this ignores the ESR step-drop. When the 50mA load is suddenly applied, the voltage instantly drops by V_drop = I × ESR. If your chosen 1.0F coin cell has a 30Ω ESR, the instant voltage drop is 0.05A × 30Ω = 1.5V. Your 3.0V rail instantly collapses to 1.5V, browning out the MCU immediately. To substitute safely, you must select a supercapacitor with an ESR low enough that the initial voltage drop keeps the rail above the MCU's minimum operating voltage, or use a lower-ESR cylindrical cell paired with a boost converter.
Failure Modes and Visual Diagnostics
Supercapacitors rarely fail dead-short like multilayer ceramic capacitors (MLCCs). Instead, they degrade parametrically or fail catastrophically via pressure relief. Recognizing these visual and electrical symptoms is critical for bench debugging and field returns.
| Failure Mode | Visual / Olfactory Symptoms | Root Cause | Bench Measurement |
|---|---|---|---|
| Electrolyte Venting | Bulging pressure relief vent on the bottom of cylindrical cells; crusty white/brown residue around seams. Sweet, acrid odor. | Overvoltage (>3.0V on a 2.7V cell) or reversed polarity causing rapid gas generation. | Open circuit or massively elevated ESR. Discard immediately. |
| Capacitance Fade & ESR Spike | No external damage. The aluminum can looks pristine and unblemished. | Operating continuously near max rated temperature (e.g., 65°C+) slowly boils off the internal solvent over years. | ESR measured at 1kHz has doubled, or capacitance dropped >30% from nameplate. |
| Pouch Swelling | The flat prismatic pouch looks like an inflated pillow; casing seams are stressed. | Moisture ingress through compromised seals, or chronic overvoltage causing water electrolysis inside the cell. | Capacitance may read normal initially, but self-discharge rate will be extremely high. |
| Terminal Corrosion | Green/white oxidation creeping up the nickel or tinned copper leads. | High humidity environment combined with minor electrolyte weeping from the seal. | Increased contact resistance; can cause intermittent connection in high-vibration applications. |
Real-World Implementation: Active vs. Passive Balancing
Because individual supercapacitor cells are limited to ~2.7V, building a 12V or 24V pack requires wiring them in series. This introduces a critical failure vector: leakage current mismatch. In a series string, Cell A might leak 1µA while Cell B leaks 5µA. Over days, the lower-leakage cell will slowly charge past its 2.7V maximum limit, leading to venting, while the higher-leakage cell remains undercharged. As detailed in Analog Devices technical articles, balancing is mandatory for any series string.
Passive Balancing:
This involves placing a simple 10kΩ to 100kΩ resistor across each individual cell. It continuously bleeds off excess voltage, forcing the cells to equalize. While cheap and easy to implement, it burns several milliamps continuously. This is acceptable for a UPS that is constantly plugged in, but it will drain a battery-backed system in days.
Active Balancing:
For high-reliability, low-power, or battery-backed systems, you must use an active balancing IC (such as the TI BQ33100 or Analog Devices LTC3350). These chips use switched-capacitor networks or inductor-based charge shuttling to move energy from the highest-voltage cell to the lowest-voltage cell only when an imbalance is detected. The parasitic draw is in the microamp range, preserving your system's energy budget while preventing overvoltage failures.
When designing your PCB layout for series supercapacitors, keep the high-current pulse traces wide and short to minimize parasitic inductance, and route the balance sense lines as Kelvin connections directly to the cell terminals—not to the shared high-current bus—to ensure the balancing IC reads the true cell voltage without I-R drop errors.






