An SMPS switching power supply transfers energy via discrete, high-frequency packets (typically 100 kHz to 2 MHz) rather than burning excess voltage as heat. By rapidly toggling a MOSFET between fully-on and fully-off states, the system minimizes resistive losses. For a 24V/5A load drawn from a 28V battery bus, a modern SMPS operates at 90-95% efficiency, whereas a linear regulator would require a massive heatsink to survive the thermal load. This guide breaks down the math, topologies, and a concrete 24V/5A buck design to get your power stage from schematic to bench test.

Linear vs. SMPS Switching Power Supply: The Headroom and Heat Math

The decision between a linear regulator and an SMPS switching power supply comes down to dropout voltage, headroom, and thermal dissipation. Linear regulators act as variable resistors; they must drop the excess input voltage across a pass transistor. The power dissipated as heat is strictly a function of the voltage differential and the load current: P_diss = (V_in - V_out) × I_load.

Consider a 24V nominal LiFePO4 battery system charging up to 28.8V, powering a 24V/5A telemetry load.

  • Linear Regulator Path: At peak charge (28.8V in, 24V out, 5A load), the regulator dissipates (28.8 - 24) × 5 = 24 Watts. Assuming a standard TO-220 package with a junction-to-ambient thermal resistance (θ_JA) of 50°C/W without a heatsink, the junction temperature would rise 1200°C above ambient—instantly triggering thermal shutdown or destroying the silicon. Even with a massive heatsink dropping θ_JA to 5°C/W, you are still dumping 24W of useless heat into your enclosure.
  • SMPS Path: A synchronous buck SMPS switching power supply operating at 94% efficiency draws roughly 127.6W from the source to deliver 120W to the load. The total system dissipation is only 7.6W, spread across the inductor's DCR (DC resistance), the MOSFETs' R_DS(on), and the PCB traces.

The Rule of Thumb: If (V_in - V_out) × I_load > 1.5W, or if your input voltage can drop below the required output voltage plus the linear regulator's dropout threshold (usually 1V to 2V), you must use a switching topology.

Topology Selection and Performance Matrix

Choosing the right SMPS topology dictates your efficiency ceiling, electromagnetic interference (EMI) profile, and component cost. Below is a data-dense comparison of the four most common non-resonant topologies used in DC/DC battery and solar systems.

Topology Efficiency Range Heat Profile Output Ripple/Noise Relative Cost Primary Use Case
Buck (Step-Down) 92% - 96% Low (Spread across L & FETs) 20mV - 50mV p-p $ Battery bus to logic/motor rails
Boost (Step-Up) 88% - 94% Medium (High peak currents) 30mV - 80mV p-p $ Solar panel MPPT front-ends
SEPIC 80% - 88% High (Dual inductor losses) 50mV - 100mV p-p $$ Wide-input buck-boost (auto 12V)
Flyback (Isolated) 75% - 85% High (Leakage inductance snubbers) 100mV - 200mV p-p $$$ Isolated gate drivers, medical

Ripple and Noise Expectations: In a buck converter, output ripple is dominated by the inductor's AC current interacting with the output capacitor's Equivalent Series Resistance (ESR). You can expect 20-50mV peak-to-peak noise. Flyback converters, however, suffer from transformer leakage inductance, which generates high-frequency ringing (often 50MHz+) that requires aggressive RC snubbers to tame. For sensitive RF or ADC loads, a buck SMPS followed by a high-PSRR (Power Supply Rejection Ratio) LDO is the standard practice to achieve sub-5mV noise floors.

24V/5A Buck SMPS Design Example: Specs, Parts, and Protection

Let's design a robust 24V/5A buck SMPS switching power supply for an industrial 24V nominal battery system. As of 2026, while integrated GaN drivers are pushing switching frequencies past 5MHz for ultra-compact consumer electronics, silicon MOSFETs in the 300kHz range remain the cost-to-reliability sweet spot for ruggedized 24V/48V systems.

Safety Warning: 24V and 48V battery banks can deliver thousands of amps under a dead short. Always use insulated tools, wear safety glasses, and install a Class T or ANL fuse at the battery terminal before connecting any prototype SMPS to the bus.

Input Protection and Range

The input must handle 18V (deep discharge sag) to 36V (alternator load dump).

  • Reverse Polarity: Use a P-channel MOSFET (e.g., SI2301) instead of a standard diode. A diode wastes 0.7V × 5A = 3.5W; a P-FET with an R_DS(on) of 50mΩ wastes only 1.25W.
  • Transient Suppression: Place a 36V TVS diode (e.g., SMAJ36A) immediately after the input fuse to clamp inductive load dumps from long cable runs.

Core Component Selection

We will use the TI TPS54560B, a 60V input, 5A continuous synchronous buck controller. Its wide input range easily survives 24V system transients.

  • Switching Frequency (f_sw): Set to 300 kHz via the RT resistor pin to balance inductor size against switching losses.
  • Inductor Sizing: Target a 30% ripple current (ΔI_L = 1.5A). Using the formula L = (V_out × (1 - D)) / (f_sw × ΔI_L) where Duty Cycle (D) = 24V / 32V (nominal) = 0.75.
    L = (24 × 0.25) / (300,000 × 1.5) = 13.3 µH.
    Select a standard 15 µH shielded ferrite inductor (e.g., Würth Elektronik 74477415) rated for at least 7A saturation current.
  • Output Capacitors: Ripple voltage is dictated by ESR. To hit < 15mV ripple, we need an ESR below 10mΩ. Use three 100µF 35V low-ESR polymer capacitors in parallel. Each has an ESR of ~15mΩ, yielding a combined ESR of 5mΩ. Expected ripple: 1.5A × 0.005Ω = 7.5mV.

Thermal and Derating Notes

The TPS54560B has a junction-to-ambient thermal resistance (θ_JA) of roughly 20°C/W when mounted on a 4-layer PCB with thermal vias under the exposed pad. At full load (120W out, 94% efficient), the IC itself dissipates about 2.5W (the rest is in the inductor and external routing). This results in a 50°C temperature rise above ambient. If your enclosure ambient hits 60°C, the silicon sits at 110°C. The IC's thermal shutdown is 170°C, so you have headroom, but you must derate the maximum continuous current by 20% if the ambient environment exceeds 65°C to ensure long-term electrolytic capacitor survival.

PCB Layout, Hot Loops, and Verification

The schematic is only half the battle in an SMPS switching power supply; the PCB layout determines whether your board runs silently or acts as a broadband RF jammer. The most critical concept is the hot loop.

In a buck converter, the hot loop is the path from the input capacitor, through the high-side MOSFET, through the low-side MOSFET (or catch diode), and back to the input capacitor's ground. This loop carries high di/dt (rapidly changing current). You must minimize the physical area of this loop to reduce parasitic inductance, which otherwise causes massive voltage ringing (V = L × di/dt) that can punch through the MOSFET's drain-source breakdown voltage.

Layout Trick: Place the ceramic input bypass capacitor (typically 1µF to 4.7µF X7R) as physically close to the IC's VIN and PGND pins as possible. Route the connection on the top layer; do not use vias to drop to an inner layer for this specific high-frequency path.

Measuring Ripple Correctly

When verifying your output noise, never use the standard 6-inch ground clip on your oscilloscope probe. That clip acts as an antenna, picking up the radiated magnetic field from the inductor and showing you 500mV of phantom noise. Instead, use a tip-and-barrel probe adapter, or solder a twisted pair of 22 AWG wire directly across the output capacitor terminals and probe the twisted pair. As noted in Analog Devices' research on Silent Switcher technology, proper probe technique often reveals that a 'noisy' supply is actually a victim of poor measurement methodology rather than poor design.

By respecting the headroom math, selecting the right topology for your noise constraints, and tightly routing your hot loops, your SMPS switching power supply will deliver clean, efficient power to your loads without turning your enclosure into an oven.