A series RLC circuit places a resistor (R), inductor (L), and capacitor (C) in a single continuous conductive loop driven by an alternating current (AC) voltage source. Unlike parallel configurations, the same current flows through all three components, making the total impedance the vector sum of the resistance and the net reactance ($X_L - X_C$). When drafting a series RLC circuit diagram, you are essentially building a frequency-dependent voltage divider that can act as a bandpass or bandstop filter, depending on where you measure the output.
Topology and Node-by-Node Behavior
To analyze the circuit on a bench, we break the loop down into four distinct nodes. Understanding the phase relationship at each node is critical for oscilloscope probing.
- Node 1 (Source+ to R): The AC signal enters the resistor. The voltage drop across R ($V_R$) is strictly in phase with the circuit current.
- Node 2 (R to L): The junction between the resistor and inductor. Here, the current begins to lag the applied voltage as the inductor's magnetic field builds.
- Node 3 (L to C): The junction between the inductor and capacitor. The voltage across the inductor ($V_L$) leads the current by 90°. This is often the point of highest voltage potential in high-Q circuits.
- Node 4 (C to Source-/GND): The capacitor returns the loop to ground. The voltage across the capacitor ($V_C$) lags the current by 90°, perfectly opposing $V_L$ at resonance.
Behavior Table: What Changes When One Element Changes?
| Component Changed | Effect on Resonant Freq ($f_r$) | Effect on Q-Factor | Effect on Bandwidth (BW) |
|---|---|---|---|
| Increase R | No change | Decreases | Widens |
| Increase L | Decreases | Increases (if R is constant) | Narrows |
| Increase C | Decreases | Decreases | Widens |
Series vs. Parallel: Topology Selection and Failure Modes
Why choose a series topology over a parallel RLC tank? The decision hinges on your impedance requirements at resonance and how the circuit handles fault conditions. A series RLC circuit exhibits minimum impedance at resonance (acting as a bandpass filter when measuring across R), while a parallel RLC circuit exhibits maximum impedance (acting as a bandstop/notch filter across the tank). For a deeper mathematical breakdown of these phase interactions, refer to the All About Circuits textbook chapter on series resonance.
Failure-Mode Contrast: What Breaks at the Extremes?
When prototyping, component failures or breadboard shorts will yield drastically different results depending on the topology. Here is what happens when a series RLC circuit hits extreme fault conditions:
- Shorted Resistor (R=0): The theoretical Q-factor approaches infinity. At resonance, the circuit becomes a dead short across the AC source, drawing massive current that will likely melt the inductor windings or trip your power supply's overcurrent protection.
- Open Resistor: The loop is broken. Current drops to absolute zero regardless of frequency.
- Shorted Inductor: The circuit degrades into a simple high-pass RC filter. Resonance is destroyed because $X_L$ can no longer cancel $X_C$.
- Open Capacitor: The loop is broken for AC, and DC is inherently blocked. The circuit ceases to function entirely.
Design Walkthrough: 15.9 kHz Bandpass Filter
Let's design a practical series RLC bandpass filter targeting an ultrasonic or audio crossover frequency of roughly 15.9 kHz. We will take the output voltage across the resistor ($V_R$). You can verify the underlying formulas for this configuration via Electronics Tutorials.
1. Pick the Inductor (L):
We select a standard 10 mH axial inductor (e.g., Bourns 78F103K-RC, approx. $1.50).
2. Calculate the Capacitor (C):
Using the resonant frequency formula $f_r = 1 / (2\pi\sqrt{LC})$, we solve for C:
$C = 1 / ((2\pi \times 15915)^2 \times 0.01) \approx 10 \text{ nF}$ (0.01 µF).
We select a 10 nF C0G/NP0 ceramic capacitor (e.g., KEMET C315C103K5G5TA5, approx. $0.20) for its low equivalent series resistance (ESR) and thermal stability.
3. Pick the Resistor (R) and Calculate Q:
We choose a 100 Ω metal film resistor (e.g., Vishay MRS25 series).
$Q = (1/R) \times \sqrt{L/C} = (1/100) \times \sqrt{0.01 / 10 \times 10^{-9}} = 0.01 \times 1000 = 10$.
Bandwidth ($BW$) = $f_r / Q = 15915 / 10 = 1591.5 \text{ Hz}$.
That 10 mH inductor isn't ideal; it has a DC resistance (DCR) of roughly 5 Ω. This parasitic resistance adds to your 100 Ω resistor, making the true $R_{total}$ 105 Ω. This drops your actual Q-factor to 9.5 and slightly widens your bandwidth. Always measure your inductor's DCR with a multimeter before finalizing your bandwidth calculations.
Step-by-Step Breadboard Testing Procedure
To validate the design on the bench, you need a function generator (e.g., Siglent SDG1032X) and an oscilloscope (e.g., Rigol DS1054Z). Follow these steps to map the Bode plot:
- Layout the Loop: Insert the 100 Ω resistor, 10 mH inductor, and 10 nF capacitor in a continuous series string across the breadboard's power rails. Keep leads short to minimize stray inductance.
- Connect the Source: Attach the function generator's BNC-to-alligator clip to Node 1 (Resistor input) and Node 4 (Capacitor ground). Set the generator to output a 2V peak-to-peak (Vpp) sine wave.
- Probe the Input and Output: Connect Oscilloscope Channel 1 to Node 1 (input) and Channel 2 to Node 2 (the junction between R and L, measuring the voltage drop strictly across the resistor to ground). Note: Ensure both scope probes share a common ground reference.
- Find Resonance: Sweep the function generator frequency from 5 kHz to 30 kHz. Watch Channel 2. The voltage amplitude on Ch2 will peak exactly at the resonant frequency (approx. 15.9 kHz). Record this exact peak frequency.
- Measure the -3dB Points: Calculate 70.7% of your peak voltage (the -3dB point). Sweep the frequency downward until Ch2 hits this voltage; record as $f_{low}$. Sweep upward until it hits this voltage again; record as $f_{high}$.
- Verify Bandwidth: Subtract $f_{low}$ from $f_{high}$. If your measured BW is close to 1.59 kHz, your component tolerances are tight and parasitic effects are well-managed.
Frequently Asked Questions
How do I calculate the resonant frequency from a series RLC circuit diagram?
The resonant frequency ($f_r$) in Hertz is calculated using the formula $f_r = 1 / (2\pi\sqrt{LC})$. Notice that the resistor (R) is entirely absent from this equation. The resistor dictates the bandwidth and the damping (Q-factor) of the circuit, but it does not shift the center frequency where the inductive reactance ($X_L$) perfectly cancels the capacitive reactance ($X_C$).
What happens to a series RLC circuit at DC (0 Hz)?
At DC, the frequency is zero. The inductor acts as a short circuit (zero reactance, limited only by its wire DCR), but the capacitor acts as a perfect open circuit (infinite reactance). Therefore, once the capacitor charges to the applied DC voltage, steady-state current drops to absolute zero. A series RLC circuit inherently blocks DC.
Why is the voltage across the inductor higher than the source voltage at resonance?
This is a phenomenon known as resonant voltage magnification. At resonance, the source voltage is only driving the resistance (R), but the circulating current ($I = V_{source} / R$) flows through L and C. The voltage across the inductor is $V_L = I \times X_L$. If the Q-factor is 10, the voltage across the inductor (and the capacitor) will be exactly 10 times higher than the source voltage. This is why high-Q series circuits require capacitors and inductors rated for voltages far exceeding the supply rail.
Can I use a series RLC circuit diagram for high-power RF applications?
Yes, but with strict component derating. In RF applications (e.g., antenna matching networks), the circulating currents at resonance can be massive. Standard through-hole ceramic capacitors will shatter from thermal stress, and small-gauge inductors will melt. For high-power RF, you must use air-wound inductors (to avoid core saturation) and high-vacuum or heavy-duty ceramic doorknob capacitors rated for high RF currents and elevated voltages.
