The series equivalent capacitance ($C_{eq}$) of two or more capacitors connected end-to-end is always strictly less than the smallest individual capacitor in the string. For two identical 100nF capacitors in series, the equivalent capacitance is exactly 50nF. The governing formula for $n$ capacitors is $1/C_{eq} = 1/C_1 + 1/C_2 + ... + 1/C_n$. While parallel configurations are used to bulk up energy storage, series configurations are the standard engineering solution for voltage stacking—allowing lower-voltage, physically smaller, and cheaper components to safely handle high-voltage rails.
The Series Topology: Node Labels and Electrical Behavior
To analyze a series capacitor string, we must define the nodes. Consider a simple two-capacitor string connected across a DC voltage source ($V_{total}$):
- Node A: The high-side input terminal (connected to the positive rail and the first lead of C1).
- Node B: The floating junction (connected to the second lead of C1 and the first lead of C2). This node stores no net charge but develops a voltage potential relative to ground based on the capacitive voltage divider ratio.
- Node C: The low-side output terminal (connected to the second lead of C2 and the ground/return rail).
Unlike resistors in series (where resistance adds), capacitance in series drops. Furthermore, the voltage divides inversely proportional to the capacitance value ($V_x = V_{total} \times C_{eq} / C_x$). The table below details the exact parameter behavior when you configure standard components in this topology.
| Parameter | Series Behavior (vs. Single Component) | Design Impact & Real-World Example |
|---|---|---|
| Capacitance ($C_{eq}$) | Decreases. Bounded by the smallest value in the string. | Two 220nF caps yield 110nF. Useful for trimming precise timing values in 555 oscillator circuits without buying 1% tolerance parts. |
| Voltage Rating ($V_{max}$) | Increases. Nominally additive if values are identical. | Two 50V rated X7R MLCCs in series can theoretically block 100V, allowing use of cheap 0805 SMD parts on a 75V bus. |
| Equivalent Series Resistance (ESR) | Adds linearly ($ESR_{eq} = ESR_1 + ESR_2$). | Increases total power dissipation ($I^2R$) in high-ripple switching converters. Requires thermal derating. |
| Equivalent Series Inductance (ESL) | Adds linearly, but physical loop area matters more. | Stacking 0805 caps in series increases the PCB trace loop area, potentially worsening high-frequency impedance compared to a single 1206 cap. |
| Leakage Current ($I_{leak}$) | Dominated by the component with the lowest leakage (highest insulation resistance). | Creates severe DC voltage imbalance. Mandates the use of parallel bleeder resistors in high-voltage designs. |
Element Change Behavior and Extreme Failure Modes
Understanding how the circuit reacts when a single element drifts or fails is critical for reliability engineering. In a parallel bank, a shorted capacitor takes down the whole rail. In a series string, the failure mechanics are distinctly different.
| Change in C1 | Effect on $C_{eq}$ | Effect on Voltage Across C1 ($V_{C1}$) | System Consequence |
|---|---|---|---|
| C1 value increases | Decreases slightly (asymptotes toward C2's value) | Decreases (C1 takes a smaller share of $V_{total}$) | Safe. C2 takes more voltage; verify C2's $V_{max}$ isn't exceeded. |
| C1 value decreases (e.g., DC bias derating) | Decreases | Increases (C1 takes a larger share of $V_{total}$) | Dangerous. X7R ceramics lose capacitance under DC bias. C1 may over-voltage and fail. |
| C1 Shorts | $C_{eq}$ becomes exactly equal to C2 | Drops to 0V | C2 instantly absorbs 100% of $V_{total}$. If $V_{total} > V_{max(C2)}$, C2 will likely avalanche and short, cascading the failure. |
| C1 Opens | $C_{eq}$ drops to 0F (Open Circuit) | Absorbs 100% of $V_{total}$ | Circuit stops functioning (no AC coupling / no energy storage). No cascade failure, but system goes dead. |
Why choose series over parallel? You choose parallel when you need to increase total energy storage ($E = \frac{1}{2}CV^2$) or reduce ESR for high-ripple filtering. You choose series when your DC bus voltage exceeds the maximum rated voltage of physically available or economically viable capacitors. For example, finding a 10µF, 250V film capacitor is expensive and physically massive. Stringing five 50µF, 50V MLCCs in series yields 10µF at a theoretical 250V rating, fitting into a fraction of the PCB footprint for a fraction of the cost.
For a deeper mathematical breakdown of capacitive voltage dividers, the All About Circuits textbook chapter on series and parallel capacitors provides excellent foundational derivations.
Design Walkthrough: Stacking MLCCs for a 100V Snubber
Let's design a 100V DC-blocking snubber network using surface-mount components. We need a final value of roughly 100nF capable of withstanding 100V continuous DC with transient spikes up to 120V.
Never simply place two 50V capacitors in series on a 100V rail and walk away. Multilayer Ceramic Capacitors (MLCCs) with X7R dielectrics suffer from severe DC bias derating—a 220nF cap might act like 110nF at 50V. Furthermore, insulation resistance varies wildly between batches. Without balancing, one cap might drop 30V while the other drops 70V, destroying the 50V-rated part.
Step 1: Select the Capacitors
We will use the KEMET C0805C224K5RAC (220nF, 50V, X7R, 0805 package). To account for X7R DC bias derating (which can drop capacitance by up to 50% at rated voltage), we oversize the nominal value. Two 220nF caps in series will yield a nominal 110nF, which under a 50V bias per cap will realistically settle around 70nF to 80nF—perfect for our snubber target.
Step 2: Calculate and Add Bleeder Resistors
To force equal voltage sharing across Node B, we place high-value resistors in parallel with each capacitor. We need the current through the resistors to be at least 10x the worst-case leakage current of the capacitors. The KEMET X7R insulation resistance is typically >100 GΩ·µF, meaning leakage is in the single-digit nanoamp range. A 1MΩ resistor (e.g., Yageo RC0805FR-071ML) will draw roughly 50µA at 50V, completely swamping the nanoamp leakage and guaranteeing a 50/50 voltage split.
Step 3: Final Schematic Netlist
- C1: KEMET C0805C224K5RAC (Node A to Node B)
- R1: Yageo 1MΩ 0805 (Node A to Node B)
- C2: KEMET C0805C224K5RAC (Node B to Node C)
- R2: Yageo 1MΩ 0805 (Node B to Node C)
This configuration guarantees that during steady-state DC, Node B sits at exactly $V_{total}/2$. During high-frequency AC transients, the capacitors dominate the impedance, and the series equivalent capacitance handles the snubbing action. For more on MLCC derating behaviors, refer to Electronics Tutorials' guide on series capacitance and manufacturer application notes.
Step-by-Step Breadboard Testing and Verification
Before committing a series capacitor design to a printed circuit board, validate the voltage division and equivalent capacitance on a breadboard using through-hole equivalents (e.g., 220nF 50V dipped radial ceramics) and an LCR meter or digital multimeter (DMM).
- Prep the Components: Insert the two 220nF capacitors into the breadboard. Connect the positive lead of C1 to Rail A (Node A). Connect the negative lead of C1 and the positive lead of C2 to a shared central bus (Node B). Connect the negative lead of C2 to Rail C (Node C / Ground).
- Install Bleeder Resistors: Insert two 1MΩ resistors. Place R1 across the same rows as C1 (Node A to Node B). Place R2 across the same rows as C2 (Node B to Node C).
- Verify $C_{eq}$ (De-energized): Set your LCR meter to measure capacitance at 1kHz (standard for MLCCs) or 120Hz (standard for electrolytics). Place the probes on Node A and Node C. Expected reading: ~110nF (±10% for standard tolerance parts). If your meter reads 'OL' or infinite, check for a bad breadboard contact at Node B.
- Verify Bleeder Network Resistance: Switch your DMM to resistance mode. Probe Node A to Node C. You should read exactly 2MΩ (the sum of R1 and R2 in series). This confirms both resistors are making solid contact and the DC path is intact.
- Apply DC Voltage and Measure Division: Connect a bench power supply set to 40V DC across Node A (positive) and Node C (negative). Do not exceed the 50V rating of the individual test capacitors.
- Probe the Junction: Set your DMM to DC Voltage. Place the black probe on Node C and the red probe on Node B. Expected reading: 20.0V (±0.5V). Move the red probe to Node A to verify the total 40V. If Node B reads significantly higher or lower than 20V (e.g., 28V), one of your capacitors has an internal leakage defect or your breadboard contacts are introducing parallel leakage paths. Clean the board and swap the suspect capacitor.
By following this topology, calculating for DC bias derating, and physically verifying the node voltages, you can reliably deploy series equivalent capacitance networks in high-voltage power electronics without risking catastrophic dielectric breakdown.
