An XOR (Exclusive OR) gate is a digital logic gate that outputs a HIGH (1) signal only when its inputs are in different logic states. If you are studying a schematic diagram of XOR gate circuits, you are looking at the fundamental building block for inequality detection and binary addition. Unlike a standard OR gate—which outputs HIGH if any or both inputs are HIGH—the XOR gate strictly requires one HIGH and one LOW input to trigger. Beginners commonly confuse it with the standard OR gate (which allows both inputs to be HIGH) or the XNOR gate (which outputs HIGH when inputs match). In a real circuit, an XOR gate changes a signal's routing by acting as a hardware-controlled inverter or a phase detector, flipping a binary bit based on a control line without requiring software intervention.
The Core Logic and Schematic Symbols
On a schematic diagram, the XOR gate symbol looks similar to a standard OR gate (a D-shape with a curved input side and a pointed output side), but it features a secondary curved line placed slightly in front of the input side. This double-curve is the universal visual indicator for "exclusive."
The Boolean expression for an XOR gate with inputs A and B and output Y is written as:
Y = A ⊕ B
This translates to the following truth table, which you should memorize if you are debugging digital logic on a bench:
| Input A | Input B | Output Y | Logic State |
|---|---|---|---|
| 0 | 0 | 0 | LOW |
| 0 | 1 | 1 | HIGH |
| 1 | 0 | 1 | HIGH |
| 1 | 1 | 0 | LOW |
According to Electronics Tutorials, the XOR function can also be expressed using standard AND, OR, and NOT gates: Y = (A AND NOT B) OR (NOT A AND B). This expanded form is exactly how the internal transistor-level schematic of an XOR IC is constructed.
Deconstructing the Schematic Diagram of XOR Gate ICs
You will rarely build an XOR gate from discrete transistors on a PCB. Instead, you will use integrated circuits (ICs) that package multiple XOR gates into a single silicon die. The most common schematic diagram of an XOR gate IC you will encounter is the Quad 2-Input XOR package, which contains four independent XOR gates in a 14-pin DIP or SOIC footprint.
Internally, a CMOS XOR gate is typically built using a network of NAND or NOR gates to minimize transistor count and propagation delay. A classic discrete-gate equivalent of an XOR requires four 2-input NAND gates. When reading a complex FPGA or ASIC schematic, the synthesis tool will often reduce XOR logic down to these fundamental NAND structures to optimize silicon area.
Worked Example: Timing and Power in a 74HC86
Let’s look at the real-world numbers for the industry-standard SN74HC86 (a quad XOR gate from Texas Instruments). Suppose you are designing a high-speed parity checker running at 10 MHz, powered by a 5V bench supply, with a standard 15pF capacitive load on each output pin.
1. Propagation Delay ($t_{pd}$)
The TI SN74HC86 datasheet lists the typical propagation delay at 5V and 15pF load as 14ns. If your 10 MHz clock has a period of 100ns, a 14ns delay consumes 14% of your timing budget per gate. If you cascade three XOR gates in a ripple-carry adder, your total delay is 42ns, leaving only 58ns for setup and hold times on the receiving flip-flops.
2. Dynamic Power Dissipation
CMOS gates draw negligible current when static, but they draw current while switching to charge and discharge the load capacitance. The formula for dynamic power per gate is:
P = C_L × V_CC² × f
- C_L (Load Capacitance) = 15pF (15 × 10⁻¹² F)
- V_CC (Supply Voltage) = 5V
- f (Switching Frequency) = 10 MHz (10 × 10⁶ Hz)
P = (15 × 10⁻¹²) × (25) × (10 × 10⁶) = 3.75 mW per gate.
For a full 74HC86 package with all four gates switching simultaneously, the dynamic power is 15 mW. Add the quiescent power (typically 20µA × 5V = 0.1mW), and the chip dissipates roughly 15.1 mW. This is well within the thermal limits of a standard DIP package, meaning no heatsink or thermal vias are required on your PCB.
Where You Meet XOR Gates in Practice
While microcontrollers handle most logic in modern hobbyist projects, XOR gates remain critical in specific hardware-level applications where software latency is unacceptable.
Half-Adders and Full-Adders
The XOR gate is the "sum" generator in binary addition. If you add 1 and 1 in binary, the sum is 0 and the carry is 1. The XOR gate naturally outputs 0 when both inputs are 1, perfectly handling the sum bit, while an AND gate handles the carry bit.
Quadrature Encoder Decoding
When reading rotary encoders, XOR gates are used to detect phase shifts between the A and B channels. By feeding the encoder outputs into an XOR gate, the output pulses only when the channels are in different states, effectively doubling the resolution of the encoder (edge detection) without writing interrupt service routines in code.
Controlled Inverters
If you tie one input of an XOR gate to a data signal and the other input to a control line, the gate acts as a programmable inverter. If the control line is LOW, the data passes through unchanged (0⊕0=0, 1⊕0=1). If the control line is HIGH, the data is inverted (0⊕1=1, 1⊕1=0). This is heavily used in motor driver H-bridge logic to flip direction signals.
IC Selection Decision Tree: Which XOR Chip to Buy
Walking into a supplier like Digi-Key or Mouser and searching for "XOR gate" yields hundreds of results. Use this decision path to select the exact part number for your workbench.
| Criteria | 74HC86 (Standard CMOS) | 74LVC86A (Low Voltage) | CD4030B (Legacy 4000 Series) |
|---|---|---|---|
| Operating Voltage | 2.0V to 6.0V | 1.2V to 3.6V | 3.0V to 18.0V |
| Propagation Delay | ~14ns @ 5V | ~4.5ns @ 3.3V | ~120ns @ 5V |
| Output Drive | ±25mA | ±24mA | ±6.8mA (Weak) |
| Best Use Case | 5V Arduino / Breadboard | 3.3V ESP32 / Raspberry Pi | High voltage / 9V-12V logic |
| Typical Price (1pc) | $0.60 - $0.90 | $0.70 - $1.10 | $0.50 - $0.80 |
If you are building 5V logic circuits or learning on a standard breadboard, buy the SN74HC86. It is the undisputed default for 5V systems.
If you are interfacing with 3.3V microcontrollers like the ESP32 or Raspberry Pi Pico, buy the SN74LVC86A (or 74LVX86). Do not feed 5V into a 74LVC chip, and do not rely on the 74HC86 to reliably read 3.3V HIGH thresholds without pull-up resistors.
Avoid the CD4030B unless you are repairing vintage synthesizers or working with 12V+ automotive logic; its slow switching speed and weak output drive make it frustrating for modern digital prototyping.
Frequently Asked Questions
Can I make an XOR gate using only NAND gates?
Yes. You can construct a functional XOR gate using exactly four 2-input NAND gates (like the 74HC00). The schematic involves feeding inputs A and B into the first two NAND gates, tying their other inputs to logic HIGH (or tying A and B together), and then feeding those outputs into a third NAND gate, which finally feeds into a fourth NAND gate alongside the original A and B signals. It is a common exercise in digital logic courses, but on a real PCB, it wastes board space and increases propagation delay compared to a dedicated 74HC86.
What happens if I leave an XOR gate input floating?
In CMOS logic (like the HC or LVC families), a floating input acts as an antenna. It will pick up electromagnetic noise, causing the internal transistors to rapidly switch back and forth between HIGH and LOW. This leads to massive current spikes, overheating the chip, and erratic output behavior. Always tie unused XOR inputs to GND or VCC via a 10kΩ resistor, or directly if the datasheet permits.
Is an XOR gate the same as a parity generator?
An XOR gate is the component used to build a parity generator. A single XOR gate generates parity for 2 bits. To check parity for an 8-bit byte, you cascade seven XOR gates together (or use a dedicated parity generator IC like the 74HC280). The XOR gate outputs a 1 if the number of HIGH inputs is odd, which is the exact definition of odd parity.
