Redundancy Law Boolean Algebra: Simplifying Logic Circuits & Avoiding Hazards

The redundancy law in Boolean algebra states that if a term is the logical product of the remaining variables from two other terms that contain a variable and its complement, that third term is logically redundant and can be eliminated without changing the circuit's output. When you are mapping out combinational logic on a whiteboard, optimizing a discrete logic PCB, or writing Verilog for an FPGA, this theorem—frequently called the consensus theorem—is your primary tool for stripping out unnecessary gates and tightening propagation delays.

The Core Mechanics of the Redundancy Law

In standard Sum of Products (SOP) form, the redundancy law is expressed algebraically as:

AB + A'C + BC = AB + A'C

Here, the term BC is the consensus term. It is formed by multiplying the uncomplemented variables (B and C) left over after the variable A and its complement A' are stripped from the first two terms. The law dictates that this consensus term adds no new logical conditions to the output; it is entirely covered by the existing boundaries of AB and A'C.

According to foundational digital logic principles outlined by Electronics Tutorials, applying this law is a mandatory step in minimizing Karnaugh maps and Quine-McCluskey algorithms before a design is committed to silicon.

Worked Numeric Example: Gate Count and Propagation Delay

To see what this changes in a real circuit, let us build the unsimplified expression Y = AB + A'C + BC using standard 74HC-series CMOS logic ICs, and then compare it to the simplified Y = AB + A'C.

The Unsimplified Circuit (Y = AB + A'C + BC):

• Inverters: 1x 74HC04 (Hex Inverter) to generate A'. (Uses 1 of 6 gates).
• AND Gates: 1x 74HC08 (Quad 2-Input AND) to generate AB, A'C, and BC. (Uses 3 of 4 gates).
• OR Gates: 1x 74HC32 (Quad 2-Input OR). Since we have three terms to OR together, we must cascade two OR gates: (AB + A'C) + BC. (Uses 2 of 4 gates).
• Total ICs: 3 physical chips (or 3 SOIC-14 footprints on a PCB).
• Worst-Case Propagation Delay: Inverter (~10ns) + AND (~14ns) + OR (~14ns) + second OR (~14ns) = 52ns total path delay.

The Simplified Circuit (Y = AB + A'C):

• Inverters: 1x 74HC04 (Uses 1 of 6 gates).
• AND Gates: 1x 74HC08 to generate AB and A'C. (Uses 2 of 4 gates).
• OR Gates: 1x 74HC32 to combine them. (Uses 1 of 4 gates).
• Total ICs: Still 3 physical chips, but we are using less than half the internal gates. In a complex design, this freed-up silicon allows you to fit an entirely different sub-circuit onto the same 74HC08 and 74HC32 packages, reducing BOM costs and board space.
• Worst-Case Propagation Delay: Inverter (~10ns) + AND (~14ns) + OR (~14ns) = 38ns total path delay.

By applying the redundancy law, we shave 14 nanoseconds off the critical path and free up three logic gates for other tasks.

Where You Meet This In Practice (And When to Break the Law)

In a textbook or an introductory logic design class, you are taught to always eliminate the redundant consensus term to save hardware. However, in high-speed digital design—such as routing a 100MHz+ clock domain in an FPGA or designing a fast discrete logic bus—blindly applying the redundancy law can introduce a catastrophic bug known as a static-1 hazard.

A static-1 hazard occurs when the output of a combinational circuit is supposed to remain at a logic '1' during an input transition, but momentarily glitches to '0' due to unequal propagation delays in the logic paths.

Let us look at the hazard in our simplified circuit (Y = AB + A'C):

1. Assume the inputs are A=1, B=1, C=1. The output Y is 1 (driven by the AB term).
2. Now, A transitions from 1 to 0. The new state is A=0, B=1, C=1. The output Y should remain 1 (now driven by the A'C term).
3. However, the A'C path requires A to pass through an inverter. This adds roughly 10ns of delay before A' becomes valid.
4. During that 10ns window, the AB term has already dropped to 0, but the A'C term has not yet risen to 1. Both inputs to the final OR gate are briefly 0.
5. The output Y glitches to 0 for a few nanoseconds before recovering.

If this Y signal is feeding a clock enable pin or an asynchronous reset line, that nanosecond glitch will trigger a false state change, crashing the system. As noted in advanced digital design literature on All About Circuits, the standard engineering fix for this specific hazard is to intentionally break the redundancy law and add the consensus term back in. By keeping BC in the equation, the BC term evaluates to 1 (since B=1 and C=1) and holds the OR gate high during the 10ns inverter delay window, completely masking the glitch.

Common Confusions: Logical vs. Hardware Redundancy

When discussing this topic on the bench, makers and junior engineers frequently confuse logical redundancy with hardware redundancy. They are entirely different concepts serving different masters.

• Logical Redundancy (Boolean): This refers to extra terms in a Boolean equation (like the BC consensus term) that do not alter the steady-state truth table. We manipulate logical redundancy to optimize gate count or eliminate timing hazards.
• Hardware Redundancy (Fault Tolerance): This refers to duplicating physical components to ensure system survival if a part fails. The classic example is Triple Modular Redundancy (TMR), used heavily in aerospace and automotive ECUs. In TMR, three identical logic circuits process the same inputs, and a majority-voter circuit outputs the consensus. If one circuit suffers a single-event upset (SEU) from radiation, the other two outvote it.

Another common mix-up is confusing the redundancy law with the absorption law. Absorption (A + AB = A) eliminates a term that is a subset of another term. Redundancy eliminates a term that is the intersection of two other terms. Both reduce gate count, but their algebraic triggers are distinct.