The most versatile and widely used circuit of an amplifier for general-purpose voltage gain is the Common Emitter (CE) BJT topology with voltage-divider bias. While operational amplifiers dominate modern board-level design, discrete BJT amplifiers remain essential for RF front-ends, ultra-low-noise audio preamps, and high-temperature environments where silicon op-amps fail. A properly biased CE stage provides both high voltage and current gain, yielding the highest power gain of the three basic BJT configurations.
This guide walks through the exact component selection, DC bias math, and failure-mode analysis for a 1kHz audio preamp stage using a standard 2N3904 NPN transistor. We will establish a stable quiescent operating point (Q-point) and detail exactly what happens when components drift or fail.
Topology and Node Definitions
The voltage-divider biased CE amplifier relies on a specific node structure to maintain thermal stability and predictable AC gain. Before selecting components, we must define the circuit nodes and their roles:
- VCC (Supply Node): The positive DC rail (9V in our design). Must be decoupled with a bulk capacitor (e.g., 10µF) and a high-frequency bypass (100nF) to prevent motorboating (low-frequency oscillation).
- Node A (Divider Midpoint): The junction of R1 and R2. Sets the DC base voltage (Vb). The current flowing through this divider must be at least 10 times the expected base current (Ib) to make Vb stiff and independent of the transistor's beta (β) variations.
- Node B (Base): The input to the transistor. Receives the AC signal via a coupling capacitor (Cin) superimposed on the DC bias voltage.
- Node C (Collector): The output node. The AC signal is extracted here via Cout. The DC voltage at this node (Vc) dictates the maximum symmetrical output swing before clipping.
- Node D (Emitter): The reference node for the transistor's internal junctions. Contains the emitter resistor(s) to ground, providing DC negative feedback for thermal stability.
Design Walkthrough and Component Behavior
Let’s design a 1kHz microphone preamp stage. Our target parameters are: VCC = 9V, Quiescent Collector Current (Ic) ≈ 1mA, and a stable, predictable AC Voltage Gain (Av) ≈ -25. We are using the ON Semiconductor 2N3904, which has a typical β of 100 to 300 at 1mA. We will assume a conservative β of 100 for our worst-case bias calculations.
1. Setting the Emitter and Base Bias
To achieve 1mA of collector current (Ic ≈ Ie), we need a 1V drop across the emitter resistor. Therefore, Re_total = 1V / 1mA = 1kΩ. The base voltage (Vb) must be one diode drop (0.7V) higher than the emitter, so Vb = 1.7V.
To make the base voltage "stiff," the divider current should be ~10x the base current. With β=100 and Ic=1mA, Ib = 0.01mA. Our target divider current is 0.1mA. Using standard E24 resistor values, we select R2 = 15kΩ and R1 = 68kΩ. This yields a real-world Vb of 1.62V, resulting in an Ie of 0.92mA—close enough to our 1mA target.
2. Setting the Collector Load and Gain
To control the AC gain and prevent clipping, we split the 1kΩ emitter resistance into an unbypassed swamping resistor (Re1 = 100Ω) and a bypassed resistor (Re2 = 910Ω). The bypass capacitor (Ce) shorts Re2 to ground at AC, leaving only Re1 and the transistor's internal emitter resistance (re ≈ 27Ω) to set the gain.
For a gain of ~25, we need Rc = 3.3kΩ. This drops about 3V across the collector resistor, leaving Vc at roughly 6V, providing ample headroom for a 3V peak-to-peak output swing.
| Component | Designator | Value / Rating | Purpose |
|---|---|---|---|
| R1 (Upper Bias) | 68kΩ, 1/4W | Sets base voltage with R2 | |
| R2 (Lower Bias) | 15kΩ, 1/4W | Sets base voltage with R1 | |
| Rc (Collector Load) | 3.3kΩ, 1/4W | Converts AC current to AC voltage | |
| Re1 (Swamping) | 100Ω, 1/4W | Stabilizes AC gain, unbypassed | |
| Re2 (DC Bias) | 910Ω, 1/4W | Sets DC Q-point, AC bypassed | |
| Ce (Bypass) | 10µF, 16V | Shorts Re2 to GND at 1kHz | |
| Cin / Cout (Coupling) | 1µF, 16V | Blocks DC, passes AC audio |
3. Behavior Matrix: Sensitivity to Component Drift
Understanding how the circuit reacts to component variations is critical for troubleshooting. The table below details the exact node behavior when a single element drifts from its design value.
| Element Changed | Effect on Vc (DC) | Effect on Ve (DC) | Effect on AC Gain | Physical Reason |
|---|---|---|---|---|
| Rc increases (e.g., 4.7k) | Drops significantly | No change | Increases (until saturation) | Higher voltage drop across Rc limits collector swing. |
| Re2 increases (e.g., 1.2k) | Rises toward VCC | Rises | No change (if Ce is intact) | Higher Ve reduces Vbe, cutting back Ic. AC ground remains. |
| Re1 increases (e.g., 220Ω) | Slight rise | Slight rise | Drops by ~50% | Gain is inversely proportional to unbypassed Re1. |
| Ce fails open | No change | No change | Drops to ~2.5 | Gain becomes Rc / (Re1 + Re2 + re), introducing heavy AC feedback. |
Why Common Emitter Over the Alternatives?
When designing a discrete circuit of an amplifier, you have three BJT topology choices. The Common Emitter is the default for voltage amplification, but it is important to understand why the alternatives fall short for this specific task.
- Common Collector (Emitter Follower): The output is taken from the emitter. This topology provides excellent current gain and high input impedance, but its voltage gain is strictly less than 1. It is used for impedance matching and buffering, not voltage amplification.
- Common Base: The input is applied to the emitter, and the base is grounded for AC. It offers excellent high-frequency response and voltage gain, but its current gain is ~1, resulting in very low input impedance (often under 50Ω). It is primarily used in RF cascode stages or current mirrors, not audio preamps.
- Common Emitter (Our Choice): Provides high voltage gain (set by Rc/Re) and high current gain (β). The phase inversion (180° shift between base and collector) is a minor trade-off for the massive power gain and flexible impedance characteristics it offers.
Failure Modes: What Breaks at the Extremes?
On the bench, components fail. Resistors drift open, solder bridges cause shorts, and capacitors dry out. A competent troubleshooter memorizes the DC signature of these faults. Because the DC bias network is tightly coupled, a single fault shifts every node in the circuit.
| Component | Open Fault Signature | Short Fault Signature |
|---|---|---|
| R1 (68kΩ) | Vc = 9V, Ve = 0V. Base is pulled to GND via R2. Transistor is in hard cutoff. No AC output. | Vc ≈ 0.2V, Ve ≈ 0.9V. Base is pulled directly to VCC. Transistor saturates heavily. Output clips on positive swings. |
| R2 (15kΩ) | Vc ≈ 0.2V, Ve ≈ 8.3V. Base pulled to VCC via R1. Massive base current flows, saturating the transistor and potentially overheating the base-emitter junction. | Vc = 9V, Ve = 0V. Base shorted to GND. Transistor cuts off entirely. |
| Rc (3.3kΩ) | Vc = 0V (or floating). No DC path for collector current. A multimeter might read a ghost voltage via the base-collector junction, but an oscilloscope will show a flatline. | Vc = 9V. Collector tied directly to the supply rail. AC signal is shorted to the VCC decoupling capacitor. Zero AC output. |
| Re1 + Re2 | Vc ≈ 0.2V. Emitter floats. Base-emitter junction acts as a simple diode to ground, drawing massive current until the transistor destroys itself or VCC sags. | Vc = 9V, Ve = 0V. Emitter tied to GND. Base voltage (1.62V) forward-biases the BE junction with no current limiting. Instant thermal destruction. |
Step-by-Step Breadboard Verification
Do not build the entire circuit and immediately apply an AC signal. Analog debugging requires a divide-and-conquer approach. Follow this exact sequence to verify your build.
- Build the DC Bias Network Only: Insert the 2N3904, R1, R2, Rc, Re1, and Re2. Leave Cin, Cout, and Ce out of the circuit for now. Apply 9V to the VCC rail.
- Verify DC Q-Point: Using a digital multimeter (DMM), measure the DC voltage at the Base (Node B), Emitter (Node D), and Collector (Node C) relative to ground.
- Expected Vb: ~1.62V. (If it reads 0V or 9V, check R1/R2 divider).
- Expected Ve: ~0.92V. (Vb minus the 0.7V Vbe drop).
- Expected Vc: ~5.9V. (VCC minus the drop across Rc). If Vc is near 9V, the transistor is off. If Vc is under 1V, it is saturated.
- Install the Bypass Capacitor (Ce): Power down, insert the 10µF Ce across Re2, and power back up. Verify that the DC voltages have not changed. (A leaky electrolytic capacitor will pull Ve down and shift your bias).
- Inject the AC Signal: Connect a function generator set to 1kHz, 20mV peak-to-peak sine wave through Cin to the base. Connect an oscilloscope probe to the collector (Node C) via Cout.
- Measure and Calculate Gain: Observe the output waveform. You should see a ~500mV peak-to-peak sine wave, inverted 180° relative to the input. If the waveform is flattened at the top or bottom (clipping), your Q-point is off, or your input signal is too large. Calculate actual gain: Av = Vout_pp / Vin_pp.
By isolating the DC bias from the AC signal path, you eliminate 90% of the common breadboarding errors—such as floating grounds, backward electrolytic capacitors, and incorrect transistor pinouts (remember, for a standard TO-92 2N3904 with the flat side facing you, the pins are Emitter, Base, Collector from left to right).
