What Is a Positive Temperature Coefficient in Power Electronics?

When you ask what is a positive temperature coefficient (PTC) on the bench, the answer splits into two distinct but equally critical domains: semiconductor physics and circuit protection. In physics, a positive temperature coefficient means a material's electrical resistance increases as its temperature rises.

For power MOSFETs, this PTC behavior applies to the on-state resistance, $R_{DS(on)}$. As the silicon junction heats up, $R_{DS(on)}$ climbs. This is actually a massive advantage over Bipolar Junction Transistors (BJTs), which have a negative temperature coefficient (NTC) and will suffer thermal runaway if paralleled. Because MOSFETs are PTC, if you parallel two of them, the hotter one naturally increases in resistance, shedding current to the cooler one and self-balancing the load.

However, this PTC trait comes with a thermal penalty: your conduction losses at 100°C are significantly higher than the datasheet's optimistic 25°C spec. The second domain where PTC matters is PTC thermistors (Polymeric Positive Temperature Coefficient devices, or PPTCs). These are resettable fuses. Under normal temps, their polymer matrix is conductive. If a fault causes them to heat past their trip point, the polymer expands, breaking the conductive carbon chains and spiking resistance by several orders of magnitude, effectively opening the circuit until the fault clears and the part cools.

Bench Rule of Thumb: For standard silicon MOSFETs, assume $R_{DS(on)}$ will be 1.5x to 2.0x its 25°C datasheet value when the junction is sitting at 100°C to 125°C. Always use the hot resistance for thermal calculations, not the cold one.

Thermal Path Math: Junction-to-Ambient Rtheta Calculations

Let's ground this in real math. Suppose you are switching a 15A continuous DC load using an Infineon IRLZ44N logic-level MOSFET in a TO-220 package. The ambient temperature inside your enclosure is 40°C.

ParameterDatasheet Value (25°C)Calculated Hot Value (100°C)
$R_{DS(on)}$ at $V_{GS}$ = 5V0.022 Ω~0.035 Ω (using 1.6x PTC multiplier)
$R_{\theta JC}$ (Junction-to-Case)1.5 °C/W1.5 °C/W
$R_{\theta JA}$ (Junction-to-Ambient, no sink)62 °C/W62 °C/W

First, calculate the actual power dissipation ($P_D$) at the elevated temperature using $I^2R$:

$P_D = 15A^2 \times 0.035\Omega = 225 \times 0.035 = 7.87 Watts

If you run this bare TO-220 without a heatsink, the temperature rise above ambient is:

$\Delta T = P_D \times R_{\theta JA} = 7.87W \times 62 °C/W = 487.9 °C

Add that to your 40°C ambient, and your junction is at 527°C. The part will violently destruct in milliseconds. You need a heatsink. We treat the thermal path like a series electrical circuit:

$R_{\theta JA(total)} = R_{\theta JC} + R_{\theta CS} + R_{\theta SA}$

Where $R_{\theta CS}$ (Case-to-Sink) is roughly 0.5 °C/W using a standard silicone thermal pad (like Bergquist Sil-Pad 2000). To find the required Sink-to-Ambient ($R_{\theta SA}$) rating, we first need to define our maximum allowed junction temperature.

Derating Curves and "How Hot Is Too Hot?"

The IRLZ44N datasheet lists an absolute maximum junction temperature ($T_{J(max)}$) of 175°C. But how hot is too hot for practical reliability? If you design to 175°C, you are designing for immediate failure.

Failure Signatures of Thermal Stress: Operating consistently above 150°C accelerates electromigration. You will see bond wire lift-off (where the microscopic aluminum wires connecting the silicon die to the pins tear away due to CTE mismatch), package cracking from epoxy outgassing, and eventual silicon melting or shorting.

Interpreting the power derating curve on page 4 of the datasheet shows linear derating from 25°C to 175°C. For a robust industrial or continuous-duty DIY design, 125°C is the practical hard ceiling. This gives you a 50°C safety margin for transient spikes and ambient fluctuations.

Let's calculate the required $R_{\theta SA}$ to keep $T_J$ at or below 125°C:

  • Allowed $\Delta T = T_{J(max)} - T_{Ambient} = 125°C - 40°C = 85°C$
  • Required $R_{\theta JA(total)} = 85°C / 7.87W = 10.8 °C/W$
  • Required $R_{\theta SA} = 10.8 - 1.5 (JC) - 0.5 (CS) = 8.8 °C/W$

You need a heatsink with a thermal resistance of 8.8 °C/W or lower in natural convection.

Heatsink Selection and Airflow: What Actually Buys You Margin

Looking at real-world extruded aluminum heatsinks for a TO-220 package, a standard 15mm long clip-on like the Wakefield-Vette 623-15AB sits around 13.5 °C/W in free air. That's too hot; it will push your junction past 140°C.

To hit our 8.8 °C/W target in natural convection, we need more mass and surface area. The Aavid Thermalloy 577202B03300G (a 20mm long, board-mountable extruded sink) provides roughly 7.5 °C/W in still air. This brings our total $R_{\theta JA}$ down to 9.5 °C/W, resulting in a junction temperature of roughly 114°C. We have margin.

What do airflow and enclosure changes buy you?
If your enclosure is sealed, you are relying purely on natural convection. If you add a 40mm fan (like a Sunon MagLev MF40101VX) pushing 200 Linear Feet per Minute (LFM) of air across the fins, the Aavid heatsink's effective $R_{\theta SA}$ drops from 7.5 °C/W to roughly 3.5 °C/W. Your junction temp plummets to ~73°C. However, fans introduce a mechanical point of failure. For high-reliability solid-state designs, oversizing the passive heatsink is always preferred over relying on active airflow.

Decision Tree: Sizing Your Thermal Management and PTC Protection

Use this decision path to finalize your thermal and protection strategy for power switching circuits.

Condition / MetricIf True...Action / Component Pick
Calculated $T_J$ > 125°C in free airPassive cooling is insufficientAdd extruded heatsink (Target $R_{\theta SA}$ < calculated limit)
Heatsink footprint exceeds PCB spacePhysical constraints block passive massSwitch to forced air (200 LFM minimum) or a D2PAK surface-mount part on a heavy copper pour
Paralleling multiple MOSFETsPTC $R_{DS(on)}$ aids current sharingEnsure symmetrical gate drive traces; no source resistors strictly needed for thermal balancing
Load is inductive (motors, relays)Inductive kickback causes voltage spikesAdd a snubber or freewheeling diode; thermal math must account for switching losses, not just $I^2R$
Protecting low-voltage logic rails (3.3V/5V)Short circuits can melt PCB tracesAdd a PPTC resettable fuse (e.g., Bourns MF-MSMF050-2 for 500mA hold)

The Default Recommendation:
If you are designing a 10A to 20A continuous DC switch on a standard FR4 board in a 40°C ambient environment, do not trust the 25°C $R_{DS(on)}$ spec. Calculate your losses using a 1.6x PTC multiplier. For the IRLZ44N at 15A, terminate your design with the Aavid Thermalloy 577202B03300G heatsink, mated with a Bergquist Sil-Pad 2000 thermal interface material. Protect your 5V microcontroller gate-drive rail with a Bourns MF-MSMF050-2 PTC resettable fuse to ensure a shorted logic rail doesn't leave your MOSFET gate floating and partially turned on (which would cause catastrophic linear-mode thermal runaway).

For deeper reading on MOSFET power dissipation and thermal impedance, refer to Texas Instruments application note SLPA018 on calculating power dissipation, and the Bourns PTC Resettable Fuses design guide for selecting the correct trip curves for your logic protection.