The standard PFET (P-channel MOSFET) symbol features three main terminals—Gate (G), Drain (D), and Source (S)—with an arrow on the Source leg pointing outward away from the channel. This outward arrow is the definitive visual identifier distinguishing it from an NFET (arrow pointing inward) and indicates conventional current flow from Source to Drain when the gate voltage is pulled sufficiently below the source voltage. Whether you are designing a high-side power switch or debugging a bricked motherboard, correctly interpreting this symbol and its physical pinout is non-negotiable.
The Complete PFET Symbol & Pinout Reference Table
Before wiring up a discrete P-channel MOSFET like the ubiquitous Si2301 or the through-hole IRF9540N, map the schematic symbol to the physical package. The table below bridges the gap between the drawing on your screen and the component on your bench.
| Symbol Element / Pin | Schematic Representation | Physical & Electrical Meaning | Standard SOT-23 Pinout |
|---|---|---|---|
| Gate (G) | Line perpendicular to channel, no direct electrical connection (capacitive coupling). | Control terminal. Pulling voltage below Source (Vgs < Vth) creates the P-type inversion channel. | Pin 1 |
| Source (S) | Line connecting to channel with an outward-pointing arrow. | Entry point for conventional current. Tied to the P-type substrate/body in standard discrete parts. | Pin 2 |
| Drain (D) | Line connecting to channel opposite the Source, no arrow. | Exit point for conventional current. Connects to the load in high-side switching configurations. | Pin 3 |
| Channel Line | Dashed line: Enhancement mode (normally OFF). Solid line: Depletion mode (normally ON). |
Indicates the default state of the silicon channel with 0V on the gate. 99% of hobbyist PFETs are enhancement mode. | N/A (Internal) |
| Body Diode | Triangle and bar superimposed between Drain and Source (Anode at Drain, Cathode at Source). | Intrinsic parasitic diode. In a PFET, it conducts if Drain voltage exceeds Source voltage. | Spans Pins 2 & 3 |
Standard Variants: IEEE vs. IEC Schematic Conventions
Schematic capture software like KiCad, Altium, or EasyEDA will offer multiple symbol libraries. The variations you see are not errors; they reflect different international drafting standards.
- IEEE 315 (US Standard): This is the most explicit variant. It draws the physical substrate connection (often internally tied to the Source) and relies on the arrow on the Source leg to define the polarity. The arrow points in the direction of conventional current flow across the PN junction (from P-type source to N-type body). For a PFET, this means the arrow points out toward the Source terminal.
- IEC 60617 (International Standard): IEC symbols often simplify the physical structure. You will frequently see a small circle (an inversion bubble) placed on the Gate line. This circle indicates that the device is "active low"—meaning a low logic signal turns it on. While the source arrow is still technically part of the standard, many IEC-derived library parts drop it in favor of the gate bubble and a simple "P" text annotation next to the channel.
- Four-Terminal (IC Design) Variants: In custom silicon or specific RF applications, the Body (B) or Substrate is not internally tied to the Source. The symbol will show a fourth pin connected to the back of the channel. In discrete power design, this is rare, but you will see it in SPICE models and IC layout schematics.
Symbol Details and Pinouts People Get Wrong
Even experienced makers drop the ball on a few specific PFET details. Here are the most common bench and design errors.
1. The Arrow Direction Memory Trap
The most common mistake is confusing NFET and PFET symbols on a quick glance. Use the industry-standard mnemonic: "P is Pointing out" (the arrow points away from the channel). Conversely, "N is iN" (the arrow points into the channel). If you wire a PFET backwards because you misread the arrow, the intrinsic body diode will forward-bias immediately, bypassing your gate control and potentially shorting your power rail.
2. Ignoring the Body Diode Orientation
In a PFET symbol, the body diode's anode is at the Drain and the cathode is at the Source. When using a PFET as a high-side switch (Source to VCC, Drain to Load), the diode is reverse-biased when the FET is off. If you accidentally swap Drain and Source in your physical layout, the diode points directly from VCC to the Load, meaning your load is permanently powered regardless of the Gate signal. For a deep dive on MOSFET parasitics, refer to the SparkFun MOSFET Tutorial.
3. Blindly Trusting SOT-23 Pin 1
The standard SOT-23 pinout for a MOSFET is Pin 1 = Gate, Pin 2 = Source, Pin 3 = Drain. However, this is a convention, not a law of physics. Parts like the DMG2305UX follow this, but some specialized or older RF FETs swap the Drain and Source pins to optimize PCB trace routing. Always pull the specific manufacturer datasheet before finalizing your footprint.
Safe Interpretation of Faded or Missing SMD Markings
SOT-23 and SOT-223 packages are notorious for laser-etched markings that rub off during rework, or for being so small they require a microscope to read. If you have a bin of unmarked SMD transistors and need to separate the PFETs from the NFETs, do not guess. Use your multimeter.
- Set your multimeter to Diode Test mode. This mode outputs a small voltage (usually 2V to 3V) and measures the forward voltage drop across a semiconductor junction.
- Identify the pins. Assume the standard SOT-23 layout (1=G, 2=S, 3=D) for testing purposes, holding the component with the text side facing you and pins pointing down.
- Test for a PFET: Place the Red probe on Pin 3 (Drain) and the Black probe on Pin 2 (Source). A healthy PFET will show a forward voltage drop between 0.40V and 0.70V. Swapping the probes should read "OL" (Open Loop).
- Test for an NFET: Place the Red probe on Pin 2 (Source) and the Black probe on Pin 3 (Drain). A healthy NFET will read 0.40V to 0.70V.
If you get "OL" in both directions across the Drain and Source, the internal body diode is blown (open). If you get ~0.00V or a continuous beep, the FET is shorted and dead. This diode test is the ultimate source of truth when schematic symbols and physical markings fail you. For more on semiconductor junction testing, the All About Circuits Semiconductor Textbook provides excellent foundational theory.
Frequently Asked Questions
How do I tell a PFET symbol from an NFET symbol at a glance?
Look at the arrow on the Source terminal. If the arrow points outward (away from the center channel line), it is a PFET. If it points inward (toward the channel), it is an NFET. Additionally, PFET symbols in IEC libraries often feature a small inversion circle on the Gate line, indicating that a low logic signal turns the device on, whereas NFETs turn on with a high logic signal.
What does the circle on the gate of some PFET symbols mean?
The circle is a logic inversion bubble borrowed from digital gate symbols. Because a P-channel MOSFET requires the Gate voltage to be lower than the Source voltage to conduct (a negative Vgs), it is considered an "active-low" device. The bubble visually reminds the circuit designer that pulling the gate to ground (0V) turns the switch ON, while pulling it high (to VCC) turns it OFF.
Why does my PFET schematic symbol have four pins instead of three?
A four-pin symbol explicitly breaks out the Body (or Substrate) terminal. In 99% of discrete through-hole and SMD MOSFETs (like the IRF9540N), the manufacturer internally connects the Body to the Source, resulting in a three-pin physical package. However, in integrated circuit (IC) design, custom silicon, or specific high-frequency RF applications, the body is left floating or tied to a different potential to manage the body effect and threshold voltage shifting. If you are working with discrete board-level components, you can safely ignore the fourth pin and treat it as a standard 3-terminal device.
Can I use a PFET as a low-side switch?
Technically yes, but practically it is a terrible idea. To turn on a PFET, the Gate must be significantly lower than the Source. If used on the low side (Source tied to Load, Drain to Ground), the Source voltage will float near ground when off, requiring a negative gate voltage relative to ground to turn it on. This requires complex charge pump circuitry. Always use PFETs for high-side switching (Source to VCC) and NFETs for low-side switching (Source to GND).
